MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 462

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.4
The polychannel is the main control unit in the SEC. It implements four independent channels.
Each cryptographic task performed by the SEC is managed by a channel and makes use of one or more of
the SEC’s execution units (EUs). Control information and data pointers for a given task are stored in the
form of a descriptor (see
determines what EUs are used, how they are configured, where to fetch needed data, and where to store
the results.
The following subsections describe the operation (including descriptor processing, arbitration, and host
notification), registers, and interrupts of the polychannel.
10.4.1
10.4.1.1
To invoke a cryptographic task, the host constructs a descriptor, selects a channel, and writes a pointer to
the descriptor into the selected channel’s fetch FIFO. Each fetch FIFO can store up to 24 pointers.
10-32
Descriptor
outbound
ipsec_aes_
inbound
1001_1
1001_1
1010_1
1011_1
1100_1
raid_xor
others
tls_ssl_
tls_ssl_
dbl_crc
stream
stream
Type
gcm
Polychannel
Channel Operation
Channel Descriptor Processing
Length
Length
Length
Length
Length Header In
Extent
Extent
Extent
Extent
Extent
field
type
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Context In
MAC Key
MAC Key
Source F
reserved
reserved
reserved
reserved
Dword0
Data In
Header
Pointer
AES
ICV
Section 10.3.1, “Descriptor
Table 10-10. Descriptor Format Summary (continued)
Payload ICV
Cipher IV In Cipher Key Main Data
Cipher IV In Cipher Key
Payload In
Source E
reserved
reserved
reserved
reserved
Dword1
Data In
Pointer
AAD In
Nonce Part
Source D
reserved
reserved
reserved
reserved
reserved
ICV Out
Dword2
Data In
Header
Pointer
2 In
Structure”) placed in system memory. A descriptor
Hash-only
Hash-only
Source C
reserved
reserved
AES Key
reserved
Part 1 In
Payload
ICV Out
Dword3
Header
Header
Data In
Pointer
Nonce
reserved
In
In
AES ICV In
Main Data
Main Data
Source B
reserved
reserved
reserved
reserved
ICV Out
Dword4
Data In
Pointer
ICV In
In
In
AES ICV Out
Data Out
Data Out
Source A
Data Out
reserved
reserved
reserved
reserved
Dword5
ICV Out
Data In
Pointer
Freescale Semiconductor
Cipher IV Out
Cipher IV Out
Context Out
CRC ICV
Data Out
reserved
reserved
reserved
reserved
reserved
Dword6
Pointer
Cipher
In/Out