MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1245

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 19-12
19.3.3
Serial ATA provides an additional block of registers to control the interface and to retrieve interface state
information.
19.3.3.1
SStatus, shown in
and host adapter. The register conveys the interface state at the time it is read and is updated continuously
and asynchronously by the host adapter. Writes to this register have no effect.
Table 19-13
Freescale Semiconductor
Offset 0x1_8100
Reset
31–29
28–24
23–19
W
18–0
R
31–12
11–8
Bit
Bit
31
SATA Superset Registers
describes the ICC fields.
describes the SStatus fields.
SATA Interface Status Register (SStatus)
Name
ITTCV
IPM
Name
—
ITC
—
—
Figure
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Interface power management state. Indicates the current interface power management
state.
0000 Device not present or communication not established
0001 Interface in active state
0010 Interface in partial power management state
0110 Interface in slumber power management state
All other values reserved
19-13, is a 32-bit read-only register that conveys the current state of the interface
Reserved
Interrupt threshold count. The number of command completions that will raise the interrupt.
00000Implied no threshold and the interrupt will be signaled based on the threshold timer.
00001, 01111The number of command complete bits which, if set, will cause the interrupt
Reserved
Interrupt threshold timer compare value. The number of AHB ticks for which a command
complete bit has to be set before the interrupt will be signaled. A value of 0 indicates that
whenever a command complete bit is set the interrupt should be signaled.
Figure 19-13. SATA Interface Status Register (SStatus)
to be signaled.
Table 19-13. SStatus Field Descriptions
Table 19-12. ICC Field Descriptions
—
All zeros
Description
Description
12 11
IPM
8
7
SPD
Access: Read only
4
SATA Controller
3
DET
19-15
0