MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1282

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
20.4.4
The transfer type register controls the operation of data transfers. The host driver should set this register
before issuing a command followed by a data transfer, or before issuing a resume command. To prevent
data loss, the eSDHC prevents a write to the bits that are involved in the data transfer of this register while
the data transfer is active.
The host driver should check PRSSTAT[CDIHB] and PRSSTAT[CIHB] before writing to this register.
20-8
Offset: 0x00C (XFERTYP)
Reset
CMDTYP
CMDINX
•
•
W
R
Field
0–1
2–7
8–9
0 1
If PRSSTAT[CDIHB] is set, any attempt to send a command with data by writing to this register is
ignored.
If PRSSTAT[CIHB] is set, any write to this register is ignored.
—
2
Transfer Type Register (XFERTYP)
CMDINX
Reserved
Command index. These bits should be set to the command number (CMD0–63, ACMD0–63) that is specified
in bits 45–40 of the command format in the SD Memory Card Physical Layer Specification .
Command type. There are three types of special commands: suspend, resume, and abort. Clear this bit field
for all other commands.
00 Normal—other commands
01 Suspend—CMD52 for writing bus suspend in the common card control register (CCCR)
10 Resume—CMD52 for writing function select in CCCR
11 Abort—CMD12, CMD52 for writing I/O abort in CCCR
• Suspend command.
• Resume command. The host driver restarts the data transfer by restoring the registers saved before sending
• Abort command.
If the suspend command succeeds, the eSDHC assumes the SD bus has been released and it is possible
to issue the next command which uses the SDHC_DAT line. The eSDHC de-asserts read wait for read
transactions and stops checking busy for write transactions. In 4-bit mode, the interrupt cycle starts.
If the suspend command fails, the eSDHC maintains its current state, and the host driver should restart the
transfer by setting PROCTL[CREQ]. The eSDHC does not check if the suspend command succeeds or not.
It is the host driver’s responsibility to issue a normal CMD52 marked as suspend command when the
suspend request is accepted by the card, so that eSDHC can be informed that the SD bus is released and
de-assert read wait during read operation.
the suspend command and sends the resume command. The eSDHC checks for pending busy state before
starting write transfers.
If this command is set when executing a read transfer, the eSDHC stops reads to the buffer.
If this command is set when executing a write transfer, the eSDHC stops driving the SDHC_DAT line.
After issuing the abort command, the host driver should issue a software reset. (Abort transaction)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
7
CMD
TYP
8
9
SEL
Figure 20-6. Transfer Type Register (XFERTYP)
DP
10
Table 20-6. XFERTYP Field Descriptions
CICEN CCCEN —
11
12
13 14 15 16
RSP
TYP
All zeros
Description
—
25
MSB
SEL
26
DTD
SEL
27
Freescale Semiconductor
—
28
AC12
Access: Read/Write
EN
29
BCEN
30
DMA
EN
31