MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 918

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.6.3.8
eTSEC implements the AMD Magic Packet™ specification for LAN-initiated power management. This
mode is normally entered with the rest of the system in a low-power sleep mode. Software must enable
normal receive function in the Ethernet MAC, and then finally set the MACCFG2[MPEN] bit to enable
Magic Packet detection before the system enters a reduced mode. While the rest of the system is operating
in low-power mode, the enabled eTSEC continues to receive Ethernet frames, but discards them
immediately. Upon receipt of any frame whose contents contain the valid Magic Packet sequence, the
eTSEC exits out of Magic Packet mode, thus clearing MACCFG2[MPEN], and raises an error/diagnostic
interrupt through IEVENT[MAG], which causes the surrounding system to wake-up. Frames received
after Magic Packet mode has exited are received into software buffers as usual. Software can abort Magic
Packet mode by writing 0 to MACCFG2[MPEN] at any time.
AMD specify a Magic Packet™ to be any Ethernet frame containing a valid Ethernet header (Destination
and Source Addresses) and valid FCS (CRC-32), and whose payload includes the specific Magic Packet
byte sequence at any offset from the start of frame. The specific byte sequence comprises an unbroken
stream of 102 bytes, the first 6 bytes of which are 0xFFFFFF_FFFFFF, followed by 16 copies of the
MAC’s unique IEEE station address in the normal byte order for Ethernet addresses. For example, if the
station address were 0x112233_445566, then the MAC would have to receive 0xFFFFFF_FFFFFF,
0x112233_445566, ..., 0x112233_445566 in any payload to detect a Magic Packet. Only frames addressed
specifically to the MAC’s station address or a valid multicast or broadcast address can be examined for the
Magic Packet sequence.
14.6.3.9
Because collisions cannot occur in full-duplex mode, gigabit Ethernet can operate at the maximum rate. If
the rate becomes too fast for a station’s receiver, the station’s transmitter can send flow-control frames to
reduce the rate. Flow-control instructions are transferred by special frames of minimum frame size. The
length/type fields of these frames have a special value.
Table 14-152
14-170
Size [Octets]
7
1
6
6
2
Magic Packet Mode
Flow Control
lists the flow-control frame structure.
The hash table cannot be used to reject frames that match a set of selected
addresses because unintended addresses can map to the same bit in the hash
table. The receive queue filer may be used to reject frames with unintended
address hits in the hash table.
Destination address 01-80-C2-00-00-01 Multicast address reserved for use in MAC frames
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Source address
Description
Length/type
Preamble
SFD
Table 14-152. Flow Control Frame Structure
Value
88-08
NOTE
Start frame delimiter
(or MAC station address)
Control frame type
Comment
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