MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 953

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.6.8.3
In the RxBD the user initializes the E, I, and W bits in the first word and the pointer in second word. If the
data buffer is used, the eTSEC modifies the E, L, F, M, BC, MC, LG, NO, CR, OV, and TR bits and writes
the length of the used portion of the buffer in the first word. The M, BC, MC, LG, NO, CR, OV, and TR
bits in the first word of the buffer descriptor are only modified by the eTSEC if the L (last BD in frame)
bit is set. The first word of the RxBD contains control and status bits. Its formats are detailed below.
The number of buffer descriptors in a ring is set using the W bit to indicate that the next buffer wraps back
to the beginning of the ring. See
information on setting the size of the buffer ring.
Figure 14-158
The RxBD definition is interpreted by eTSEC hardware as if RxBDs mapped to C data structures in the
manner illustrated by
Freescale Semiconductor
Offset
0–1
2–3
4–7
Offset + 0
Offset + 2
Offset + 4
Offset + 6
0–15
0–31
Bits
14
15
Table 14-169. Transmit Data Buffer Descriptor (TxBD) Field Descriptions (continued)
Receive Buffer Descriptors (RxBD)
defines the RxBD.
TX Data
Length
Pointer
Name
Buffer
TOE
Data
UN
TR
E
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure
RO1
Underrun. Written by the eTSEC.
0 No underrun encountered (data was retrieved from external memory in time to send a complete
1 The Ethernet controller encountered a transmitter underrun condition while sending the
TCP/IP off-load enable. Written by user. Valid only if set in the first BD of a frame.
0 No TCP/IP off-load acceleration is applied to the frame prior to transmission.
1 eTSEC looks for a TOE Frame Control Block preceding the frame, and applies TCP/IP off-load
Truncation. Written by the eTSEC. Set in the last TxBD (TxBD[L] is set) when IEVENT[BABT]
occurs for a frame (a frame length greater than or equal to the value set in the maximum frame
length register is encountered, the HFE bit in the BD is cleared, and MACCFG2[Huge Frame] is
cleared). The frame is sent truncated.
Data length is the number of octets the eTSEC should transmit from this BD’s data buffer. It is never
modified by the eTSEC. This field must be greater than zero, as zero indicates a BD not ready.
The transmit buffer pointer contains the address of the associated data buffer. The data buffer
pointer for the first BD of a TxPAL-enabled frame must be aligned on an 8-byte boundary. There are
no alignment restrictions for the data buffer pointers of the second or subsequent BDs of a
TxPAL-enabled frame, or for non-TxPAL frames.
1
frame).
associated buffer. This could also have occurred in relation to a bus error causing
IEVENT[EBERR]. The eTSEC terminates the transmission and updates UN.
acceleration as controlled by the FCB.
W
2
14-159.
Section 14.5.3.5.5, “Maximum Frame Length Register
Figure 14-158. Receive Buffer Descriptor
3
I
L
4
F
5
RX DATA BUFFER POINTER
0
6
DATA LENGTH
M
7
Description
BC
8
MC
9
LG
Enhanced Three-Speed Ethernet Controllers
10
NO
11
SH
12
CR
13
(MAXFRM),” for
OV
14
TR
15
14-205