MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 917

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If the CRC hash table index selects a bit that is set in the hash table, the frame is accepted. If 32 group
addresses are stored in the hash table and random group addresses are received, the extended hash table
prevents roughly 480/512 (93.8%) of the group address frames from reaching memory. Software must
further filter those that reach memory to determine if they contain the correct addresses. Alternatively,
small multicast groups can be held in the exact match MAC address registers, which guarantees that only
correct frames are admitted.
The effectiveness of the hash table declines as the number of addresses increases. For instance, as the
number of addresses stored in the 512-bin hash table increases, the vast majority of the hash table bits are
set, preventing only a small fraction of frames from reaching memory.
Freescale Semiconductor
/* Wrapper macros for 256-bucket and 512-bucket hash tables:
#define TSEC_HASH256(macaddr) ((crc32(macaddr) >> 24) & 0xff)
#define TSEC_HASH512(macaddr) ((crc32(macaddr) >> 23) & 0x1ff)
/* CRC constants.
#define CRC_POLYNOMIAL 0xedb88320
#define CRC_INITIAL
#define MAC_ADDRLEN
#define BITS_PER_BYTE
/* crc32() Takes the array of bytes, macaddr[], representing an
unsigned long crc32(unsigned char macaddr[MAC_ADDRLEN])
{
}
*/
unsigned long crc, result;
int byte, i;
/* CRC-32 algorithm starts by inverting first 4 bytes */
crc = CRC_INITIAL;
/* add each byte to running CRC accumulator */
for (byte = 0; byte < MAC_ADDRLEN; ++byte) {
}
/* finally, reverse bits of result to get CRC in normal bit order */
for (result = 0, i = 4*BITS_PER_BYTE-1; i >= 0; crc >>= 1, --i)
return result;
Pass 6-byte Ethernet MAC address as parameter. */
Ethernet MAC address and returns the CRC-32 result over these bytes,
where each byte is used in bit-reversed form (Ethernet bit order).
Index 0 of macaddr[] is the first byte of the address on the wire.
Test case: the result of crc32 on {0x00, 0x01, 0x02, 0x03, 0x04, 0x05}
should be 0xad0c28f3.
crc ^= macaddr[byte];
/* shift CRC right to perform but reversal on byte of address */
for (i = 0; i < BITS_PER_BYTE; ++i)
result |= (crc & 1) << i;
crc = (crc >> 1) ^ CRC_POLYNOMIAL;
crc >>= 1;
if (crc & 1)
else
Figure 14-144. Sample C Code for Computing eTSEC Hash Table Indices
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Note: CRC-32 polynomial is bit-reversed. */
0xffffffff
6
8
Enhanced Three-Speed Ethernet Controllers
14-169