MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1461

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The channel between the host and an endpoint at a specific device represents a data pipe. Endpoint 0 for a
device is always a control type data channel used for device discovery and enumeration. Other types of
endpoints support by USB include bulk, interrupt, and isochronous. Each endpoint type has specific
behavior related to packet response and error handling. More detail on endpoint operation can be found in
the USB 2.0 specification.
The USB controller supports up to six endpoint specified numbers. The DCD can enable, disable and
configure each endpoint.
Each endpoint direction is essentially independent and can be configured with differing behavior in each
direction. For example, the DCD can configure endpoint 1-IN to be a bulk endpoint and endpoint 1-OUT
to be an isochronous endpoint. This helps to conserve the total number of endpoints required for device
operation. The only exception is that control endpoints must use both directions on a single endpoint
number to function as a control endpoint. Endpoint 0 is, for example, is always a control endpoint and uses
the pair of directions.
Each endpoint direction requires a queue head allocated in memory. If the maximum of 6 endpoint
numbers, one for each endpoint direction are being used by the device controller, then 12 queue heads are
required. The operation of an endpoint and use of queue heads are described later in this document.
21.8.3.1
After hardware reset, all endpoints except endpoint zero are uninitialized and disabled. The DCD must
configure and enable each endpoint by writing to configuration bit in the ENDPTCTRLn register. Each
32-bit ENDPTCTRLn is split into an upper and lower half. The lower half of ENDPTCTRLn is used to
configure the receive or OUT endpoint and the upper half is likewise used to configure the corresponding
transmit or IN endpoint. Control endpoints must be configured the same in both the upper and lower half
of the ENDPTCTRLn register otherwise the behavior is undefined. The following table shows how to
construct a configuration word for endpoint initialization.
21.8.3.1.1
There are two occasions where the USB controller may need to return to the host a STALL.
The first occasion is the functional stall, which is a condition set by the DCD as described in the USB 2.0
device framework (chapter 9). A functional stall is only used on non-control endpoints and can be enabled
in the device controller by setting the endpoint stall bit in the ENDPTCTRLn register associated with the
Freescale Semiconductor
Endpoint Initialization
Stalling
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-83. Device Controller Endpoint Initialization
Data Toggle Reset
Data Toggle Inhibit
Endpoint Type
Endpoint Stall
Field
1
0
00 Control
01 Isochronous
10 Bulk
11 Interrupt
0
Value
Universal Serial Bus Interfaces
21-127