MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 567

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0x3_6018
Reset
10.7.6.5
The MDEU Data Size Register, shown in
processed.
The Data Size field is a 21-bit signed number. Values written to this register are added to the current
register value. Multiple writes are allowed. The MDEU processes data when there is a positive value in
this register and there is data available in the MDEU input FIFO. (Negative values can arise in inbound
processing, when it is necessary to hold back data from the MDEU until the pad length has been
decrypted.)
Since the MDEU does not support bit offsets, bits 61–63 must be written as 0 and are always read as zero.
Furthermore, when the CONT bit of the MDEU mode register is set, the data size must be a multiple of
the block size (512 bits for MD5, SHA-1, SHA-224 and SHA-256; 1024 bits for SHA-384 and SHA-512).
Violating either of these conditions causes a data size error (DSE in the MDEU interrupt status register).
This register is cleared when the MDEU is reset or re-initialized. At the end of processing, its contents has
been decremented down to zero (unless there is an error interrupt).
10.7.6.6
This register, shown in
self-clearing bits.
Freescale Semiconductor
W
R
0
Reset
Field
Addr
R/W
MDEU Data Size Register
MDEU Reset Control Register
0
Writing to the data size register allows the MDEU to enter auto-start mode.
Therefore, the required context registers must be written prior to writing the
data size.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure
10-87, allows three levels reset of just the MDEU, as defined by the three
Figure 10-87. MDEU Reset Control Register
Figure 10-86. MDEU Data Size Register
—
Figure
10-86, specifies the number of bits of data to be
NOTE
MDEU 0x3_6010
—
All zeros
R/W
0
42
43
Data Size
Security Engine (SEC) 3.0
Access: Read/Write
60
RI MI
61
63
10-137
62
63
S
R