MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 670

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0x0_50B4
Reset
Reset
Enhanced Local Bus Controller
13.3.1.10 Transfer Error Check Disable Register (LTEDR)
The transfer error check disable register (LTEDR), shown in
checking. Note that control of error/event checking is independent of control of reporting of errors/events
(LTEIR) through the interrupt mechanism.
Table 13-17
13-28
10–11
Bits
3–4
6–7
W
W
0
1
2
5
8
9
R
R
BMD FCTD PARD
16
0
WARA Write after read atomic (WARA) error checking disable.
RAWA Read after write atomic (RAWA) error checking disable.
Name
FCTD FCM command time-out disable
PARD Parity and ECC error checking disabled. Note that uncorrectable read errors may cause the assertion of
WPD
BMD
—
—
—
describes LTEDR fields.
1
Bus monitor disable
0 Bus monitor is enabled.
1 Bus monitor is disabled, but internal bus time-outs can still occur.
0 FCM command timer is enabled.
1 FCM command time-out is disabled, but internal FCM command timer can terminate command waits.
core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled.
0 Parity and ECC error checking is enabled.
1 Parity and ECC error checking is disabled.
Reserved
Write protect error checking disable.
0 Write protect error checking is enabled.
1 Write protect error checking is disabled.
Reserved
0 WARA error checking is enabled.
1 WARA error checking is disabled.
0 RAWA error checking is enabled.
1 RAWA error checking is disabled.
Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
Figure 13-14. Transfer Error Check Disable Register (LTEDR)
3
—
4
Table 13-17. LTEDR Field Descriptions
WPD
5
6
—
—
7
All zeros
All zeros
WARA RAWA
Description
8
Figure
9
13-14, is used to disable error/event
10
—
11
CSD
12
Freescale Semiconductor
13
29
Access: Read/Write
UCCD
—
30
CCD
15
31