MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1382

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.5.4.1
DWord0 of a siTD is a pointer to the next schedule data structure.
21.5.4.2
DWords 1 and 2 specify static information about the full-speed endpoint, the addressing of the parent
Companion Controller, and micro-frame scheduling control.
21-48
1
I/O
ioc P
30–24
22–16
31
31–5
Bits
Bits
4–3
2–1
Host controller read/write; all others read-only.
31
23
0
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
Port Number
Next Link
Hub Address
Port Number
Pointer
Name
0000
Typ
Name
—
T
Next Link Pointer
siTD Endpoint Capabilities/Characteristics
I/O
—
0000_0000_0000_00000
Figure 21-38. Split-Transaction Isochronous Transaction Descriptor (siTD)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
This field contains the address of the next data object to be processed in the periodic list and
corresponds to memory address signals [31:5], respectively.
Reserved, should be cleared. These bits must be written as zeros.
Indicates to the host controller whether the item referenced is an iTD/siTD or a QH. This allows the host
controller to perform the proper type of processing on the item after it is fetched. Value encodings are:
00 iTD (isochronous transfer descriptor)
01 QH (queue head)
10 siTD (split transaction isochronous transfer descriptor
11 FSTN (frame span traversal node)
Terminate.
0 Link pointer is valid.
1 Link pointer field is not valid.
Table 21-45. Endpoint and Transaction Translator Characteristics
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Direction (I/O). This field encodes whether the full-speed transaction should be an IN or OUT.
0 OUT
1 IN
This field is the port number of the recipient transaction translator.
Reserved, should be cleared. Bit reserved and should be cleared.
This field holds the device address of the companion controllers’ hub.
Total Bytes to Transfer
0
Hub Address
Next Link Pointer
Back Pointer
Table 21-44. Next Link Pointer
1
15
µFrame C-prog-mask
0000
14 13 12 11 10
µFrame C-mask
Description
Description
EndPt
000_0000
9
1
8
Current Offset
0
7
6
µFrame S-mask
Device Address
5
Status
Freescale Semiconductor
4
TP
00
1
1
0000
3
1
2
T-count
Typ
1
T 0x00
T 0x18
0
1
0x0C
0x04
0x08
0x10
0x14
Offset