MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1363

BOARD DEV SYSTEM MPC8536E

MPC8536DS

Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets

Specifications of MPC8536DS

Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
21.3.2.15 USB Mode Register (USBMODE)—Non-EHCI
This register is not defined in the EHCI specification. This register controls the operating mode of the
module.
Freescale Semiconductor
Bits
Offset 0x1A8
2
1
0
Reset
W
R
Name
CSC
CCS
31
PE
Port enabled/disabled
Host mode:
Device mode:
Connect change status
Host mode:
1 Connect Status has changed.
0 No change.
Device mode:
Current connect status
Host mode:
1 Device is present
0 No device present.
Device mode:
1 Attached
0 Not attached.
• Ports can only be enabled by the controller as a part of the reset and enable. Software cannot enable a port
• When the port is disabled, (0) downstream propagation of data is blocked except for reset.
• This field is zero if Port Power(PP) is zero in host mode.
• The device port is always enabled. (This bit will be one).
• This bit indicates a change has occurred in the port’s Current Connect Status. the controller sets this bit for
• This field is zero if Port Power(PP) is zero.
• This bit is undefined.
• This field is zero if Port Power(PP) is zero in host mode.
• A one indicates that the device successfully attached and is operating in either high-speed or full-speed as
by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault
condition) or by the host software. Note that the bit status does not change until the port state actually
changes. There may be a delay in disabling or enabling a port due to other host and bus events.
all changes to the port device connect status, even if system software has not cleared an existing connect
status change. For example, the insertion status changes twice before system software has cleared the
changed condition, hub hardware will be ‘setting’ an already-set bit (i.e., the bit will remain set). Software
clears this bit by writing a one to it.
indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach
successfully or was forcibly disconnected by the software writing a zero to USBCMD[RS] (run bit). It does
not state the device being disconnected or suspended.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-22. PORTSC Register Field Descriptions (continued)
Figure 21-21. USB Mode (USBMODE)
All zeros
Description
5
Universal Serial Bus Interfaces
SDIS SLOM —
4
Access: Read/Write
3
2
1
CM
21-29
0

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