MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 777

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-8
Freescale Semiconductor
Bits
10
0
1
2
3
4
5
6
7
8
9
EBERR Internal bus error. This bit indicates that a system bus error occurred while a DMA transaction was
MSRO
Name
BABR
GTSC
BABT
RXC
BSY
TXC
TXE
TXB
—
describes the fields of the IEVENT register.
maximum frame length register while MACCFG2[Huge Frame] is set.
0 Excessive frame not received.
1 Excessive frame received.
Receive control interrupt. A control frame was received while MACCFG1[Rx_Flow] is set. As soon as the
transmitter finishes sending the current frame, a pause operation is performed.
0 Control frame not received.
1 Control frame received.
0 No frame received and discarded.
1 Frame received and discarded.
underway. As a result, transferred data is expected to be partially or completely invalid.
0 No system bus error occurred.
1 System bus error occurred.
Reserved
size of its register.
0 MIB count not exceeding its register size.
1 MIB count exceeds its register size.
the transmitter is put into a pause state after completion of the frame currently being transmitted.
0 No graceful stop interrupt.
1 Graceful stop requested.
MAC’s maximum frame length register and MACCFG2[Huge Frame] is cleared. Frame truncation occurs
when this condition occurs.
0 Transmitted frame length not exceeding maximum frame length.
1 Transmitted frame length exceeding maximum frame length when MACCFG2[Huge Frame] = 0.
0 Control frame not transmitted.
1 Control frame transmitted.
TSTAT[THLT] to be set by the eTSEC. This bit is set whenever any transmit error occurs that causes the
transmitter to halt (EBERR, LC, CRL, XFUN).
0 No transmit channel error occurred.
1 Transmit channel error occurred.
set in its status word and was not the last buffer descriptor of the frame.
0 No transmit buffer descriptor updated.
1 Transmit buffer descriptor updated.
Babbling receive error. This bit indicates that a frame was received with length in excess of the MAC’s
Busy condition interrupt. Indicates that a frame was received and discarded due to a lack of buffers.
MIB counter overflow. This interrupt is asserted if the count for one of the MIB counters has exceeded the
Graceful transmit stop complete. This interrupt is asserted for one of two reasons. Graceful stop means that
Babbling transmit error. This bit indicates that the transmitted frame length has exceeded the value in the
Transmit control interrupt. This bit indicates that a control frame was transmitted.
Transmit error. This bit indicates that an error occurred on the transmitted channel that has caused
Transmit buffer. This bit indicates that a transmit buffer descriptor was updated whose I (interrupt) bit was
• A graceful stop, which was initiated by setting DMACTRL[GTS], is now complete.
• A transmission of a flow control PAUSE frame, which was initiated by setting TCTRL[TFC_PAUSE], is
now complete.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-8. IEVENT Field Descriptions
Description
Enhanced Three-Speed Ethernet Controllers
14-29