MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 799

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

modified when the transmitter is disabled or when no Tx buffer is in use (after a GRACEFUL STOP
TRANSMIT command is issued and the frame completes its transmission) in order to change the next
TxBD eTSEC transmits.
Table 14-24
14.5.3.2.10 Transmit Descriptor Base Address High Register (TBASEH)
The TBASEH register is written by the user with the most significant address bits common to all TxBD
addresses, including TBASE0–TBASE7 and TBPTR0–TBPTR7. As a consequence, all TxBD rings must
be placed in a 4 Gbyte segment of memory whose base address is prefixed by the bits in TBASEH. Data
buffers are located in a potentially different region, based at TBDBPH.
TBASEH register.
Table 14-25
Freescale Semiconductor
29–31
28–31 TBASEH Most significant bits common to all TxBD addresses—except data buffer pointers. The user must initialize
0–28
0–27
Bits
Bits
Offset eTSEC1:0x2_4184+8 n ;
Reset
Offset eTSEC1:0x2_4200;
Reset
W
W
R
R
TBPTR n Current TxBD pointer for TxBD ring n . Points to the current BD being processed or to the next BD the
eTSEC3:0x2_6184+8 n
eTSEC3:0x2_6200
Name
Name
0
0
—
—
describes the fields of the TBPTRn register.
describes the fields of the TBASEH register.
transmitter uses when it is idling. When the end of the TxBD ring is reached, eTSEC initializes TBPTR n to
the value in the corresponding TBASE n . The TBPTR register is internally written by the eTSEC’s DMA
controller during transmission. The pointer increments by eight (bytes) each time a descriptor is closed
successfully by the eTSEC. Note that the three least significant bits of this register are read-only and zero.
After an error condition, the eTSEC returns TBPTR n to point to the first BD of the frame partially transmitted.
Reserved
Reserved
TBASEH before enabling the eTSEC transmit function.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 14-19. TBPTR0–TBPTR7 Register Definition
Figure 14-20. TBASEH Register Definition
Table 14-25. TBASEH Field Descriptions
Table 14-24. TBPTR n Field Descriptions
TBPTR n
—
All zeros
All zeros
Description
Description
Enhanced Three-Speed Ethernet Controllers
Figure 14-20
describes the
Access: Read/Write
Access: Read/Write
27 28
28 29
TBASEH
—
14-51
31
31