MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 369

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

These fields in the appropriate registers in the PIC must be set for self refresh to function:
See
Section 9.3.7.2, “External Interrupt Destination Registers (EIDR0–EIDR11),”
registers.
Note that this application precludes any other simultaneous use of IRQ_OUT.
8.6.3.2
The DDR controller also has a software-programmable bit, DDR_SDRAM_CFG_2[FRC_SR], that
immediately puts main memory into self-refresh mode. See
Configuration 2 (DDR_SDRAM_CFG_2),”
It is expected that a critical interrupt routine triggered by an external voltage sensing device has time to set
this bit.
8.6.3.3
The DDR controller offers an initialization bypass feature (DDR_SDRAM_CFG[BI]), which system
designers may use to prevent re-initialization of main memory during system power-on following an
abnormal shutdown. See
for information on this bit and
a discussion of avoiding possible ECC errors in this mode.
Note that the DDR controller automatically waits 200 DRAM cycles before issuing any command after
the assertion of MCKE[0:3] when this mode is used.
Freescale Semiconductor
•
•
Section 9.3.7.1, “External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11),”
EIVPRn[PRIORITY] should be set to 0xF (highest priority)
EIDRn[EP] should be set in order to route the incoming signal to IRQ_OUT
Software Based Self-Refresh
Bypassing Re-initialization During Battery-Backed Operation
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 8.4.1.8, “DDR SDRAM Control Configuration (DDR_SDRAM_CFG),”
Section 8.4.1.16, “DDR Initialization Address (DDR_INIT_ADDR),”
for a description of this register.
Section 8.4.1.9, “DDR SDRAM Control
for descriptions of these
DDR Memory Controller
and
8-95
for