MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1360

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21-26
19–16
15–14
Bits
24
23
22
21
20
WKOC Wake on over-current enable. Writing this bit to a one enables the port to be sensitive to over-current
WKDS Wake on disconnect enable. Writing this bit to a one enables the port to be sensitive to device disconnects as
WLCN Wake on connect enable. Writing this bit to a one enables the port to be sensitive to device connects as
PHCD PHY low power suspend. This bit is not defined in the EHCI specification.
Name
PFSC Port force full-speed connect. Used to disable the chirp sequence that allows the port to identify itself as a HS
PTC
PIC
port. This is useful for testing FS configurations with a HS host, hub or device.
0 Allow the port to identify itself as high speed.
1 Force the port to only connect at full speed.
This bit is not defined in the EHCI specification.
This bit is for debugging purposes.
Host mode:
Device mode:
0 Normal PHY operation.
1 Signal the PHY to enter low power suspend mode
Reading this bit indicates the status of the PHY.
Note: If there is no clock connected to the USB n _CLK signals, PHCD must be set and the following registers
should not be written: DEVICE_ADDR/PERIODICLISTBASE, PORTSC, ENDPTCTRL0, ENDPTCTRL1,
ENDPTCTRL2, ENDPTCTRL3, ENDPTCTRL4, ENDPTCTRL5.
conditions as wake-up events.
This field is zero if Port Power (PP) is zero.
This bit is (host mode only) for use by an external power control circuit.
wake-up events.
This field is zero if Port Power (PP) is zero or in device mode.
This bit is (host mode only) for use by an external power control circuit.
wake-up events.
This field is zero if Port Power(PP) is zero or in device mode.
This bit is (host mode only) for use by an external power control circuit.
Port test control. Any other value than zero indicates that the port is operating in test mode.
0000 Not Enabled.
0001 J_STATE.
0010 K_STATE.
0011 SEQ_NAK.
0100 Packet.
0101 FORCE_ENABLE.
0110–1111 Reserved, should be cleared.
Refer to Chapter 7 of the USB Specification Revision 2.0 [3] for details on each test mode.
Port indicator control. Control the link indicator signals. These signals are valid for host mode only.
00 Off.
01 Amber.
10 Green.
11 Undefined.
Refer to the USB Specification Revision 2.0 [3] for a description on how these bits are to be used.
This field is output from the module on the USB port control signals for use by an external LED driving circuit.
• The PHY can be put into low power suspend—when the downstream device has been put into suspend
• The PHY can be put into low power suspend—when the device is not running (USBCMD[RS] = 0b) or
mode or when no downstream device is connected. Low power suspend is completely under the control of
software.
suspend signaling is detected on the USB. Low power suspend will be cleared automatically when the
resume signaling has been detected or when forcing port resume.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-22. PORTSC Register Field Descriptions (continued)
Description
Freescale Semiconductor