MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 786

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 14-13
14.5.3.1.8
DMACTRL is writable by the user to configure the DMA block.
the DMACTRL register.
Table 14-14
14-38
Offset eTSEC1:0x2_402C;
Reset
17–23
16–31
0–15
Bits
0–15
Bits
16
Offset eTSEC1:0x2_4028;
Reset
W
R
eTSEC3:0x2_602C
W
0
R
Name
Name
eTSEC3:0x2_6028
PTE
0
LE
—
—
PT
describes the fields of the PTV register.
describes the fields of the DMACTRL register.
DMA Control Register (DMACTRL)
Extended pause control. This field allows software to add a 16-bit additional control parameter into the PAUSE
frame to be sent when TCTRL[TFC_PAUSE] is set. Note that current IEEE 802.3 PAUSE frame format
requires this parameter to be cleared.
Pause time value. Represents the 16-bit pause quanta (that is, 512 bit times). This pause value is used as
part of the PAUSE frame to be sent when TCTRL[TFC_PAUSE] is set. See
on page 14-170
Reserved
Little-endian descriptor mode enable. This bit controls both the reading and writing of descriptors; data
buffers are always transferred in network byte order.
0 RxBDs and TxBDs are interpreted with big-endian byte ordering, as shown in
1 RxBDs and TxBDs are interpreted with little-endian byte ordering. That is, the 16 bits of flags are
Reserved
Buffer Descriptors.”
considered a complete half-word unit, the buffer length is considered another complete half-word unit, and
the buffer pointer is considered a complete word unit.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
for more information.
PTE
Table 14-14. DMACTRL Field Descriptions
Figure 14-8. PTV Register Definition
Table 14-13. PTV Field Descriptions
Figure 14-9. DMACTRL Register
15 16 17
LE
—
All zeros
All zeros
15 16
Description
Description
23
TDSEN TBDSEN — GRS GTS TOD WWR WOP
24
Figure 14-9
25
26
Section 14.6.3.9, “Flow Control,”
describes the definition for
PT
27
Section 14.6.8.1, “Data
Freescale Semiconductor
28
Access: Read/Write
Access: Read/Write
29
30
31
31