MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 391

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.1.4
GCR, shown in
Table 9-8
9.3.1.5
VIR, shown in
zero value for VIR[VENDORID] indicates a generic OpenPIC-compliant device, which makes the other
VIR fields meaningless.
Table 9-9
Freescale Semiconductor
3–31
Offset 0x1020
Reset
Bits
Offset 0x1080
8–15
Reset
Bits
0–7
0
1
2
W
W
R
R
RST — M
0
Name
0
RST
describes the GCR fields.
describes the VIR fields.
Name
—
—
STEP
M
—
1
Global Configuration Register (GCR)
Vendor Identification Register (VIR)
Figure
Reset. Setting RST forces the PIC to be reset. Cleared automatically when the reset sequence is complete.
See
Reserved, should be cleared.
Mode. PIC operating mode.
0 Pass-through mode. On-chip PIC is disabled and interrupts detected on IRQ0 are passed directly to core
1 Mixed mode. Interrupts are handled by the normal priority and delivery mechanisms of the PIC.
Reserved, should be cleared.
2
Figure
0.
—
Reserved, should be cleared.
Stepping. Indicates the silicon revision for this device. Has no meaning if VENDOR ID value is zero.
3
Section 9.4.8, “Resetting the
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
9-7, is defined by the OpenPIC specifications and is provided for compliance. The
9-6, controls the PIC’s operating mode, and allows software to reset the PIC.
Figure 9-6. Global Configuration Register (GCR)
Figure 9-7. Vendor Identification Register (VIR)
7
8
Table 9-8. GCR Field Descriptions
Table 9-9. VIR Field Descriptions
Section 9.1.3, “Modes of
STEP
PIC,” for more information.
All zeros
All zeros
15 16
Description
Description
Operation,” provides details about these modes.
—
DEVICE ID
Programmable Interrupt Controller (PIC)
23 24
VENDOR ID
Access: Read/Write
Access: Read only
9-21
31
31