MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 66

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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lxvi
IPGIFG Register Definition ................................................................................................ 14-78
Half-Duplex Register Definition......................................................................................... 14-79
Maximum Frame Length Register Definition..................................................................... 14-80
MII Management Configuration Register Definition ......................................................... 14-80
MIIMCOM Register Definition .......................................................................................... 14-81
MIIMADD Register Definition .......................................................................................... 14-82
MII Mgmt Control Register Definition............................................................................... 14-82
MIIMSTAT Register Definition .......................................................................................... 14-83
MII Mgmt Indicator Register Definition ............................................................................ 14-83
Interface Status Register Definition .................................................................................... 14-84
MAC Station Address Part 1 Register Definition ............................................................... 14-85
MAC Station Address Part 2 Register Definition ............................................................... 14-85
MAC Exact Match Address n Part 1 Register Definition ................................................... 14-86
MAC Exact Match Address x Part 2 Register Definition ................................................... 14-86
Transmit and Receive 64-Byte Frame Register Definition ................................................. 14-88
Transmit and Receive 65- to 127-Byte Frame Register Definition .................................... 14-88
Transmit and Received 128- to 255-Byte Frame Register Definition ................................ 14-89
Transmit and Received 256- to 511-Byte Frame Register Definition................................. 14-89
Transmit and Received 512- to 1023-Byte Frame Register Definition .............................. 14-90
Transmit and Received 1024- to 1518-Byte Frame Register Definition ............................ 14-90
Transmit and Received 1519- to 1522-Byte VLAN Frame Register Definition ................ 14-91
Receive Byte Counter Register Definition.......................................................................... 14-91
Receive Packet Counter Register Definition ...................................................................... 14-92
Receive FCS Error Counter Register Definition................................................................. 14-92
Receive Multicast Packet Counter Register Definition ...................................................... 14-93
Receive Broadcast Packet Counter Register Definition ..................................................... 14-93
Receive Control Frame Packet Counter Register Definition .............................................. 14-94
Receive Pause Frame Packet Counter Register Definition ................................................. 14-94
Receive Unknown OPCode Packet Counter Register Definition ....................................... 14-95
Receive Alignment Error Counter Register Definition....................................................... 14-95
Receive Frame Length Error Counter Register Definition ................................................. 14-96
Receive Code Error Counter Register Definition ............................................................... 14-96
Receive Carrier Sense Error Counter Register Definition .................................................. 14-97
Receive Undersize Packet Counter Register Definition ..................................................... 14-97
Receive Oversize Packet Counter Register Definition ....................................................... 14-98
Receive Fragments Counter Register Definition ................................................................ 14-98
Receive Jabber Counter Register Definition....................................................................... 14-99
Receive Dropped Packet Counter Register Definition ....................................................... 14-99
Transmit Byte Counter Register Definition ...................................................................... 14-100
Transmit Packet Counter Register Definition ................................................................... 14-100
Transmit Multicast Packet Counter Register Definition ................................................... 14-101
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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