MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 867

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-110
14.5.3.9.2
The ATTRELI registers are written by the user to specify the extract index and extract length for extracting
received frames. The extract length is typically set to the expected length of extracted packet headers.
Figure 14-107
Freescale Semiconductor
17–18 ELCWT Extracted L2 cache write type. Specifies the write transaction type to perform for the extracted data. For
20–21 BDLWT Buffer descriptor L2 cache write type. specifies the write transaction type to perform for the bufferdescriptor
22–23
26–31
0–16
Bits
19
24
25
Offset eTSEC1:0x2_4BFC;
Reset
W
RBDSEN RxBD snoop enable.
R
RDSEN Rx data snoop enable.
Name
eTSEC3:0x2_6BFC
0
—
—
—
—
—
1
describes the fields of the ATTR register.
describes the definition for the ATTRELI register.
Attribute Extract Length and Extract Index Register (ATTRELI)
Reserved
maximum performance, it is recommended that if ELCWT is set to allocate, BDLWT should also be set to
allocate.Writes to cache are always performed with snoop.
00 No allocation performed.
01 Reserved
10 Allocate L2 cache line.
11 Reserved.
Reserved
for a receive frame. Writes to cache are always performed with snoop.
00 No allocation performed.
01 Reserved
10 Allocate L2 cache line.
11 Reserved.
Reserved
0 Disables snooping of all receive frames data to memory unless ELCWT specifies L2allocation.
1 Enables snooping of all receive frames data to memory.
0 Disables snooping of all receive BD memory accesses unless BDLWT specifies L2 allocation.
1 Enables snooping of all receive BD memory accesses.
Reserved
2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
EL
Figure 14-107. ATTRELI Register Definition
Table 14-110. ATTR Field Descriptions
12 13
All zeros
—
Description
17 18
Enhanced Three-Speed Ethernet Controllers
EI
25 26
Access: Read/Write
—
14-119
31