MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1391

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4
21.5.6.1
The first DWord of a queue head contains a link pointer to the next data object to be processed after any
required processing in this queue has been completed, as well as the control bits defined below.
This pointer may reference a queue head or one of the isochronous transfer descriptors. It must not
reference a queue element transfer descriptor.
21.5.6.2
The second and third DWords of a Queue Head specify static information about the endpoint. This
information does not change over the lifetime of the endpoint. There are three types of information in this
region:
The host controller must not modify the bits in this region.
Freescale Semiconductor
31–5
Bits
Offsets 0x14 through 0x27 contain the transfer results.
4–3
2–1
0
•
•
•
Endpoint characteristics. These are the USB endpoint characteristics, which include addressing,
maximum packet size, and endpoint speed.
Endpoint capabilities. These are adjustable parameters of the endpoint. They affect how the
endpoint data stream is managed by the host controller.
Split transaction characteristics. This data structure manages full- and low-speed data streams for
bulk, control, and interrupt with split transactions to USB 2.0 Hub transaction translator.
Additional fields exist for addressing the hub and scheduling the protocol transactions (for
periodic).
Name
QHLP Queue head horizontal link pointer. This field contains the address of the next data object to be processed in
Typ
—
T
Queue Head Horizontal Link Pointer
Endpoint Capabilities/Characteristics
the horizontal list and corresponds to memory address signals [31:5], respectively.
Reserved, should be cleared. These bits must be written as zeros.
Indicates to the hardware whether the item referenced by the link pointer is an iTD, siTD or a QH. This allows
the host controller to perform the proper type of processing on the item after it is fetched.
00 iTD (isochronous transfer descriptor)
01 QH (queue head)
10 siTD (split transaction isochronous transfer descriptor)
11 FSTN (frame span traversal node)
Terminate.
1 Last QH (pointer is invalid).
0 Pointer is valid.
If the queue head is in the context of the periodic list, a one bit in this field indicates to the host controller that
this is the end of the periodic list. This bit is ignored by the host controller when the queue head is in the
asynchronous schedule. Software must ensure that queue heads reachable by the host controller always
have valid horizontal link pointers.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-55. Queue Head DWord 0
Description
Universal Serial Bus Interfaces
21-57