MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1355

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.2.10 Master Interface Data Burst Size Register (BURSTSIZE)—Non-EHCI
This register is not defined in the EHCI specification. This register is used to control and dynamically
change the burst size used during data movement on the initiator (master) interface.
21.3.2.11 Transmit FIFO Tuning Controls Register (TXFILLTUNING)—Non-EHCI
This register is not defined in the EHCI specification. This register is used to control and dynamically
change the burst size used during data movement on device DMA transfers. It is only used in host mode.
The fields in this register control performance tuning associated with how the USB module posts data to
the TX latency FIFO before moving the data onto the USB bus. The specific areas of performance include
the how much data to post into the FIFO and an estimate for how long that operation should take in the
target system.
Definitions:
T
T
T
T
T
Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller checks to ensure
T
during the pre-fill operation the time remaining the [micro]frame is < T
the packet is tried at a later time. Although this is not an error condition and the module eventually
recovers, a mark is made in the scheduler health counter to note the occurrence of a back-off event. When
a back-off event is detected, the partial packet fetched may need to be discarded from the latency buffer to
make room for periodic traffic that will begin after the next SOF. Too many back-off events can waste
Freescale Semiconductor
Offset 0x160
Reset 0
31–16
s
0
1
ff
p
p
15–8
Bits
7–0
= Total Packet Flight Time (send-only) packet (T
= Standard packet overhead
= Time to send data payload
= Total Packet Time (fetch and send) packet (T
remains before the end of the [micro]frame. If so it proceeds to pre-fill the TX FIFO. If at any time
= Time to fetch packet into TX FIFO up to specified level.
W
R
31
TXPBURST Programable TX burst length. This register represents the maximum length of a burst in 32-bit words
RXPBURST Programable RX burst length. This register represents the maximum length of a burst in 32-bit words
0
Name
—
0
0
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved, should be cleared.
while moving data from system memory to the USB bus. Must not be set to greater that 16.
while moving data from the USB bus to system memory. Must not be set to greater than 16.
0
Figure 21-16. Master Interface Data Burst Size (BURSTSIZE)
0
Table 21-18. BURSTSIZE Register Field Descriptions
0
—
0
0
0
0
0
0
p
0
s
= T
= T
16 15
0
ff
0
0
+ T
Description
+ T
0
s
)
1
)
0
TXPBURST
1
0
s
then the packet attempt ceases and
0
0
8
0
Universal Serial Bus Interfaces
7
0
0
RXPBURST
0
Access: Read/Write
1
0
0
0
21-21
0
0