MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 565

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.6.3
The most common task likely to be executed by the MDEU is HMAC generation. HMACs are used to
provide message integrity within a number of security protocols, including IPsec, and TLS. The SSL 3.0
protocol uses a slightly different SSL-MAC. If an HMAC or SSL-MAC is to be performed using a single
descriptor (with the MDEU acting as sole or secondary EU), the following mode register bit settings
should be used:
Freescale Semiconductor
The following bits are controlled through the MODE0 or MODE1 fields of the descriptor header.
62-63
Bits
54
55
56
57
58
59
60
61
Recommended Settings for MDEU Mode Register
NEW (=1)
HMAC
CONT
SMAC
Name
EALG
CICV
ALG
INIT
—
Table 10-60. MDEU Mode Register in New Configuration (continued)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Determines the configuration of the MDEU Mode Register. This table shows the
configuration for NEW=1.
Reserved, must be cleared.
Continue: Most operations require this bit to be cleared. Set only when the data to be
hashed is spread across multiple descriptors.
0 Do autopadding and complete the message digest. Used when the entire hash is
1 This hash is continued in a subsequent descriptor. Do not autopad and do not complete
Compare Integrity Check Values:
0 Normal operation; no ICV checking.
1 After the message digest (ICV) is computed, compare it to the data in the MDEU’s input
Specifies whether to perform an SSL-MAC operation:
0 Normal operation
1 Perform an SSL3.0 MAC operation. This requires a key and key length. If this is set then
Initialization Bit: Most operations require this bit to be set. Cleared only for operations that
load context from a known intermediate hash value.
0 Do not initialize digest registers. In this case the registers must be loaded from a hash
1 Do an algorithm-specific initialization of the digest registers.
Specifies whether to perform an HMAC operation:
0 Normal operation
1 Perform an HMAC operation. This requires a key and key length. If this is set then the
The EALG (Extended Algorithm bit) and ALG (Algorithm) bits together specify the
message digest algorithm, as follows:
000 if MDEU-B, then SHA-384. If MDEU-A, then SHA-160 algorithm (full name for SHA-1)
001 SHA-256 algorithm
010 if MDEU-B, then SHA-512. If MDEU-A, then MD5 algorithm
011 SHA-224 algorithm
others: Reserved
performed with one descriptor, or on the last of a sequence of descriptors.
the message digest.
FIFO. If the ICVs do not match, send an error interrupt to the channel. The number of
bytes to be compared is given by the ICV size register.
the HMAC bit should be 0.
context pointer in the descriptor. When the data to be hashed is spread across multiple
descriptors, this bit is set on all but the first descriptor.
SMAC bit should be 0.
Description
Security Engine (SEC) 3.0
10-135