MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1233

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the descriptor is built, the host software locates a free command slot within the SATA controller by
examining the command queue register. To issue the command, the host software programs the address of
the command descriptor and the attributes into the appropriate command header locations and then issues
the command by writing the PMP and setting the appropriate CQ bit in the command queue register.
19.2.2
After a command is issued, the SATA controller takes ownership of the command descriptor, transferring
the command FIS to the targeted device when required, servicing the data transfer using the scatter/gather
list provided and transferring the status back into the command descriptor (if programmed).
19.2.3
When a command completes, it is possible to enable the SATA controller to generate an interrupt.
Associated with some commands there will be a command completion status FIS. The SATA controller
will always transfer the status FIS to memory whether it indicates an error or good command completion.
19.2.4
When receiving FIS’s from attached devices, the SATA controller has to support interleaving from various
devices. Data FIS’s from device 0 could be interleaved with data FIS’s for device 1. In order to accomplish
this, the SATA controller maintains in hardware a context for each command which is pushed onto and
pulled from the DMA controller when needed to service the transfers.
19.2.5
When the SATA controller receives an FIS indicating that the next operation to a particular device should
be a data write transfer, the SATA controller will lock the interface by forcing the link layer to transition
to X_RDY immediately and not go through idle SYNC. This will mean that write transfers will not have
to be interleaved, which simplifies the transmit data path and eliminates the need for a complex scheduler.
19.2.6
The SATA controller supports the reception of the DMAT primitive. When the SATA controller receives
a DMAT primitive from the device, it will perform the following actions.
The DMA controller will complete the current read burst and transfer the data to the transport layer FIFO.
The DMA controller signals an EOF on the last data of the burst, which causes the link layer to insert the
CRC and EOF. The context for this transfer is returned to the context store. Once this action is completed,
the device can terminate the transfer or re-initiate the transfer as per Serial ATA Revision 2.5 Section 9.4.4.
19.3
The function of the SATA command layer is to allow host software queue commands. It then manages the
command issue and service using context to complete the queued commands.
Freescale Semiconductor
Command Layer Overview
Command Service
Command Completion Interrupt Timing
DMA Context (Read Data)
DMA Context (Write Data)
DMAT Primitive Processing
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
SATA Controller
19-3