MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 392

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
9.3.1.6
PIR, shown in
respective core0_hreset or core1_hreset signal to assert. Note that after requesting a core reset using this
register the applicable bit should not be cleared until the requested core reset has occurred.
Note that although the OpenPIC architecture was defined to support up to 32 processing cores, only fields
corresponding to the number of cores on the device are implemented.
Table 9-10
9.3.1.7
IPIVPRs, shown in
interrupt channels. There is one vector/priority register per channel. The VECTOR and PRIORITY values
should not be changed while IPIVPRn[A] is set. See
information on IPR and ISR.
9-22
0–29
Bits Name
Offset IPIVPR0: 0x10A0; IPIVPR1: 0x10B0; IPIVPR2: 0x10C0; IPIVPR3: 0x10D0
Reset
Offset 0x1090
Reset
16–23 DEVICE ID Device identification. Vendor-specified identifier for this device. Has no meaning if VENDOR ID is zero.
24–31 VENDOR ID Vendor identification. Specifies the manufacturer of this part. A value of zero implies a generic
30
31
Bits
W
W
R
R
MSK
1
P1
P0
0
—
1
0
Reserved in single-processor implementations.
Name
describes the PIR fields.
Reserved, should be cleared.
Processor core 1 reset. Setting this bit causes the PIC to assert the core1_hreset signal. Reserved in
single-processor implementations.
Processor core 0 reset. Setting this bit causes the PIC to assert the core0_hreset signal.
A
1
0
Processor Core Initialization Register (PIR)
Interprocessor Interrupt Vector/Priority Registers (IPIVPR0–IPIVPR3)
Figure
0
2
Figure 9-9. Interprocessor Interrupt Vector/Priority Register (IPIVPR n )
0
OpenPIC-compliant device.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure
0
9-8, provides a way for software to generate a core reset. Setting P1 or P0 causes the
0
Figure 9-8. Processor Core Initialization Register (PIR)
9-9, contain the interrupt vector and priority fields for the four interprocessor
0
—
Table 9-9. VIR Field Descriptions (continued)
0
0
Table 9-10. PIR Field Descriptions
0
0
11 12
0
0
PRIORITY
0
—
0
All zeros
Section 9.4.1, “Flow of Interrupt Control,”
Description
15 16
0
Description
0
0
0
0
0
0
0
VECTOR
0
0
Freescale Semiconductor
0
0
Access: Read/Write
0
Access: Mixed
0
29
for
0
P1
30
0
1
P0
31
31
0