MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 561

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

from the base key address to write to the KEU key data registers_3 and KEU key data registers_4 while
using the KEU exclusively for the f9 integrity function.
Reading from either of these registers causes an address error, which is reflected in the KEU interrupt
status register.
10.7.5.16 KEU FIFOs
KEU uses an input FIFO/output FIFO pair to hold data before and after the encryption process. Normally,
the channels control all access to these FIFOs. For host-controlled operation, a write to anywhere in the
KEU FIFO address space enqueues data to the KEU input FIFO, and a read from anywhere in the KEU
FIFO address space de-queues data from the KEU output FIFO.
A write to the input FIFO go first to a staging register, which can be written by byte, word (4 bytes), or
dword (8 bytes). When all 8 bytes of the staging register have been written, the entire dword is
automatically enqueued into the FIFO. If any byte is written twice between enqueues, it causes an error
interrupt of type AE from the EU. When writing the last portion of data, it is not necessary to write all 8
bytes. The last bytes remaining in the staging register are automatically padded with zeros and forced into
the input FIFO when the KEU end of message register is written.
The output FIFO is readable by byte, word, or dword. When all 8 bytes of the head dword are read, the
dword is automatically dequeued from the FIFO so that the next dword (if any) becomes available for
reading. If any byte is read twice between de-queues, it causes an error interrupt of type AE from the EU.
Overflows and underflows caused by reading or writing the KEU FIFOs are reflected in the KEU interrupt
status register.
The KEU fetches data 64 bits at a time from the KEU Input FIFO. During f8 processing, the input data is
XORed with the generated keystream and the results are placed in the KEU output FIFO. During f9
processing, the input data is hashed with the integrity key and the resulting MAC is placed in the KEU data
out register. The output size is the same as the input size.
Freescale Semiconductor
Address KEU 0x3_E410
Address KEU 0x3_E418
Reset
Reset
W
W
R
R
0
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 10-79. KEU Key Data Register_3 (IK-high)
Figure 10-80. KEU Key Data Register_3 (IK-high)
Figure 10-81. KEU Key Data Register_4 (IK-low)
Figure 10-82. KEU Key Data Register_4 (IK-low)
KEU Key Data Register _3 (IK-high)
KEU Key Data Register _4 (IK-low)
All zeros
All zeros
Security Engine (SEC) 3.0
Access: Read/write
Access: Write-only
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