MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 504

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
In CMAC cipher mode the received MAC is placed in context registers 3–4, and the computed MAC is put
in registers 1–2 if AUX0=1. Context registers 5-6 are used to provide E(K, {0}
and K2 can be computed after context switch without a time penalty. The computed value of E(K, {0}
is always stored in context registers 5-6 to be available for saving context in case of context switching.
Operation of the AESU in CMAC cipher mode requires the following steps (note these steps are performed
automatically in channel-driven access):
10.7.1.11.3 Context for Confidentiality and Data Integrity Cipher Modes
The context registers for the different cipher modes which provide both confidentiality and data integrity
are summarized in
10-74
10. Read MAC from context registers 1-2
11. For CMAC with ICV, check ICCR bits in the status register
.
1. Reset
2. Program the AESU mode register as follows:
3. Load key
4. Load context
5. Set key size
6. Set ICV size for computed/received MAC (8, 10, 12, 14 or 16 bytes, default is 16)—ignored if
7. Set data size
8. While available:
9. Write to the end of message register
a.
b.
c.
d.
AUX0 = 1
a.
Table 10-31. AESU Context Registers for Modes Providing Confidentiality and Integrity
Set cipher mode to CMAC (encode/decode bit is ignored)
Set AUX0 = 1 if processing of the message is going to be interrupted and later continued after
a context switch. Set AUX0 = 0 if this is the last (or only) part of the message so that the final
MAC can be generated.
Set AUX1 = 1 for keys K1 and K2 to be derived from E(K, {0}
registers 5–6. Otherwise, set AUX1=0, and CMAC computes E(K, {0}
Set AUX2 = 1 if using CMAC with ICV.
Load data blocks
Table
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Context Register #
(byte address)
1 (0x34100)
2 (0x34108)
10-31. The registers are described in more detail in the following subsections.
Cipher Mode providing Confidentiality and Integrity
IV* / MAC
CCM
Computed MAC
128
) that is loaded into context
GCM
128
) if AUX1=1, so that K1
128
Freescale Semiconductor
).
128
)