MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1466

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.8.3.5
21.8.3.5.1
All requests to a control endpoint begin with a setup phase followed by an optional data phase and a
required status phase. The USB controller will always accept the setup phase unless the setup lockout is
engaged.
The setup lockout will engage so that future setup packets are ignored. Lockout of setup packets ensures
that while software is reading the setup packet stored in the queue head, that data is not written as it is being
read potentially causing an invalid setup packet.
The setup lockout mechanism can be disabled and a tripwire type semaphore will ensure that the setup
packet payload is extracted from the queue head without being corrupted be an incoming setup packet.
This is the preferred behavior because ignoring repeated setup packets due to long software interrupt
latency would be a compliance issue.
Setup Packet Handling
21.8.3.5.2
Following the setup phase, the DCD must create a device transfer descriptor for the data phase and prime
the transfer.
After priming the packet, the DCD must verify a new setup packet has not been received by reading the
ENDPTSETUPSTAT register immediately verifying that the prime had completed. A prime will complete
when the associated bit in the ENDPTPRIME register is zero and the associated bit in the ENDPTSTATUS
register is a one. If a prime fails, that is, The ENDPTPRIME bit goes to zero and the ENDPTSTATUS bit
is not set, then the prime has failed. This can only be due to improper setup of the dQH, dTD or a setup
21-132
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Disable Setup Lockout by writing '1' to Setup Lockout Mode (SLOM) in USBMODE. (once at
initialization). Setup lockout is not necessary when using the tripwire as described below.
After receiving an interrupt and inspecting ENDPTSETUPSTAT to determine that a setup packet
was received on a particular pipe:
— Write ‘1’ to clear corresponding bit ENDPTSETUPSTAT.
— Write ‘1’ to Setup Tripwire (SUTW) in USBCMD register.
— Duplicate contents of dQH.SetupBuffer into local software byte array.
— Read Setup TripWire (SUTW) in USBCMD register. (if set – continue; if cleared – goto 2)
— Write ‘0’ to clear Setup Tripwire (SUTW) in USBCMD register.
— Process setup packet using local software byte array copy and execute status/handshake phases.
Note: After receiving a new setup packet the status and/or handshake phases may still be pending
from a previous control sequence. These should be flushed and de-allocated before linking a new
status and/or handshake dTD for the most recent setup packet.
Control Endpoint Operation Model
Setup Phase
Leaving the Setup Lockout Mode As '0' will result in a potential compliance
issue.
Data Phase
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE
Freescale Semiconductor