MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1467

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

arriving during the prime operation. If a new setup packet is indicated after the ENDPTPRIME bit is
cleared, then the transfer descriptor can be freed and the DCD must reinterpret the setup packet.
Should a setup arrive after the data stage is primed, the device controller will automatically clear the prime
status (ENDPTSTATUS) to enforce data coherency with the setup packet.
21.8.3.5.3
Similar to the data phase, the DCD must create a transfer descriptor (with byte length equal zero) and prime
the endpoint for the status phase. The DCD must also perform the same checks of the ENDPTSETUPSTAT
as described above in the data phase.
21.8.3.5.4
Shown in the following table is the device controller response to packets on a control endpoint according
to the device controller state.
Freescale Semiconductor
The MULT field in the dQH must be set to ‘00’ for bulk, interrupt, and
control endpoints.
Error handling of data phase packets is the same as bulk packets described
previously.
Status Phase
The MULT field in the dQH must be set to ‘00’ for bulk, interrupt, and
control endpoints.
Error handling of data phase packets is the same as bulk packets described
previously.
Control Endpoint Bus Response Matrix
Token
Setup
Type
Out
In
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
STALL
STALL
Table 21-88. Control Endpoint Bus Response Matrix
Stall
ACK
Primed
ACK
NAK
NAK
Not
Endpoint State
NYET/ACK
Receive +
Transmit
Primed
NOTE
NOTE
NOTE
NOTE
ACK
3
Underflow
BS Error
N/A
N/A
2
SYSERR
Overflow
NAK
N/A
1
Universal Serial Bus Interfaces
Lockout
Setup
N/A
N/A
21-133