MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 418

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
9.3.8.1
Figure 9-45
with a bit set causes a self interrupt for a single-core device. Because external bus masters can write to
these registers, this feature can serve as a doorbell type interrupt.
Offset Processor core 0: IPIDR0: 0x0040; IPIDR1: 0x0050; IPIDR2: 0x0060; IPIDR3: 0x0070
Reset
9-48
W
R
Processor core 1
Pre-CPU offsets: IPIDR0: 0x0040; IPIDR1: 0x0050; IPIDR2: 0x0060; IPIDR3: 0x0070
1
0
Reserved in single-processor implementations.
shows the four IPIDRs, one for each interprocessor interrupt channel. Writing to an IPIDR
Interprocessor Interrupt Dispatch Register (IPIDR0–IPIDR3)
Figure 9-45. Interprocessor Interrupt Dispatch Registers (IPIDR0–IPIDR3)
Figure 9-44. Per-CPU Register Address Decoding in a Four-Core Device
Uses Core ID
Per-CPU Register
Address Decode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reg 3
1
:IPIDR0: 0x1040; IPIDR1: 0x1050; IPIDR2: 0x1060; IPIDR3: 0x1070
Reg 2
IACK Registers (one per core)
Reg 1
Reg 0
0x40
0x40
0x40
0x40
—
All zeros
ID0
ID1
Address
Normal Register
Address Decode
ID2
ID3
Freescale Semiconductor
Processor
Cores
Access: Write Only
P1
30
1
P0
31