MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1281

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.4.3
The command argument register contains the SD/MMC command argument.
Freescale Semiconductor
BLKSIZE
BLKCNT
CMDARG
16–18
19–31
Field
0–15
Field
0–31
Offset: 0x008 (CMDARG)
Reset
W
R
Block count for current transfer. This field is enabled when XFERTYP[BCEN] is set and is valid only for multiple block
transfers. The host driver should set this field to a value between 1 and the maximum block count. The eSDHC
decrements the block count after each block transfer and stops when the count reaches zero. Clearing this field
results in no data blocks being transferred.
When saving transfer context as a result of a suspend command, this field indicates the number of blocks yet to be
transferred. When restoring transfer context prior to issuing a resume command, the host driver should write the
previously saved block count.
0000 Stop count
0001 1 block
0002 2 blocks
...
FFFF 65,535 blocks
Reserved
Transfer block size. Specifies the block size for block data transfers. Values can range from one byte up to the
maximum buffer size.
The DMA always writes at least four bytes to memory. Thus, software should allocate a buffer space rounded up to
a 4-byte alighted size in order to avoid data corruption.
0000 No data transfer
0001 1 byte
0002 2 bytes
0003 3 bytes
0004 4 bytes
...
01FF 511 bytes
0200 512 bytes
...
0800 2048 bytes
1000 4096 bytes
0
Command argument. The SD/MMC command argument is specified as bits 39–8 of the command format in the SD
or MMC Specification. If PRSSTAT[CMD] is set, this register is write-protected.
Command Argument Register (CMDARG)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 20-5. Command Argument Register (CMDARG)
Table 20-4. BLKATTR Field Descriptions
Table 20-5. CMDARG Field Descriptions
Description
Description
CMDARG
All zeros
Enhanced Secure Digital Host Controller
Access: Read/Write
20-7
31