MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1247

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
15–12
Bit
27
26
25
24
23
22
21
20
19
18
17
16
11
10
Name
—
W
IN
—
—
H
C
D
N
A
X
F
S
B
E
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Port selector presence detected. This bit is set when COMWAKE is received while the host is in state
HP2: HR_AwaitCOMINIT. On power-up reset this bit is cleared. The bit is cleared when the host writes
a 1 to this bit location.
bit was cleared. The means by which the implementation determines that the device presence has
changed is vendor specific. This bit may be set anytime a PHY reset initialization sequence occurs as
determined by reception of the COMINIT signal, whether in response to a new device being inserted,
to a COMRESET having been issued, or to power-up.
Unrecognized FIS type. When set to 1, this bit indicates that since the bit was last cleared, one or more
FIS’s were received by the transport layer with good CRC, but they had a type field that was not
recognized.
Link sequence error. When set to 1, this bit indicates that one or more link state machine error
conditions were encountered since the last time this bit was cleared. The link layer state machine
defines the conditions under which the link layer detects an erroneous transition.
Handshake error. When set to 1, this bit indicates that one or more R_ERRP handshake responses
were received in response to frame transmission. Such errors may be the result of a CRC error
detected by the recipient, of a disparity or 10b/8b decoding error, or of other error conditions leading
to a negative handshake on a transmitted frame.
CRC error. When set to 1, this bit indicates that one or more CRC errors occurred with the link layer
since the bit was last cleared.
since the last time the bit was cleared.
occurred since the bit was last cleared.
COMWAKE detected. When set to 1, this bit indicates that a COMWAKE signal was detected by the
PHY since the last time this bit was cleared.
PHY internal error. When set to 1, this bit indicates that the PHY detected some internal error since
the last time this bit was cleared.
PHYRDY change. When set to 1, this bit indicates that the PHYRDY signal changed state since the
last time this bit was cleared.
and may have put the host bus adapter into an error state. Host software should reset the interface
before retrying the operation. If the condition persists, the host bus adapter may suffer from a design
issue rendering it incompatible with the attached device.
Exchanged. When set to 1 this bit indicates that device presence has changed since the last time this
Reserved.
Disparity error. When set to 1, this bit indicates that incorrect disparity was detected one or more times
10b to 8b decode error. When set to 1, this bit indicates that one or more 10-bit to 8-bit decoding errors
Reserved bit for future use; should be cleared.
E Internal error. The host bus adapter experienced an internal error that caused the operation to fail
Reserved.
Table 19-14. SError Field Descriptions (continued)
ERR Decode
Description
SATA Controller
19-17