MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1222

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Serial Peripheral Interface
enables and clearing a bit masks the corresponding interrupt. Unmasked SPIE bits must be cleared before
the core clears internal interrupt requests.
Bits RNE and TNF in SPIE are status bits. They are not cleared as a result of writing to SPIE.
shows the eSPI mask register.
Table 18-6
18-8
Offset 0x008
Reset
W
R
24–31
0–15
Bits
16
17
18
19
20
21
22
23
0
Name
describes the SPIM fields.
DON Last character transmitted mask
RNE Rx not empty interrupt mask
TXE
RXT
RXF
TXT
TNF
—
—
—
Tx FIFO empty interrupt mask
0 TXE event will not cause eSPI Interrupt
1 TXE event will cause eSPI Interrupt
0 DON event will not cause eSPI Interrupt
1 DON event will cause eSPI Interrupt
Rx threshold interrupt mask
0 RXT event will not cause eSPI Interrupt
1 RXT event will cause eSPI Interrupt
Rx FIFO full interrupt mask
0 RXF event will not cause eSPI Interrupt
1 RXF event will cause eSPI Interrupt
Tx threshold interrupt mask
0 TXT event will not cause eSPI Interrupt
1 TXT event will cause eSPI Interrupt
0 Not Empty event will not cause eSPI Interrupt
1 Not Empty event will cause eSPI Interrupt
Tx not full interrupt mask
0 Not full event will not cause eSPI Interrupt
1 Not full event will cause eSPI Interrupt
Reserved, should be cleared.
Reserved, should be cleared.
Reserved, should be cleared.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Figure 18-5. eSPI Mask Register (SPIM)
Table 18-6. SPIM Field Descriptions
15
TXE DON RXT RXF TXT — RNE TNF
16
All zeros
17
Description
18
19
20
21
22
23
24
Freescale Semiconductor
Access: Read/Write
Figure 18-5
—
31