MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1372

BOARD DEV SYSTEM MPC8536E

MPC8536DS

Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets

Specifications of MPC8536DS

Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Universal Serial Bus Interfaces
The setting of AGE_CNT_THRESH is highly dependent on both the mix of other controllers operating on
the system bus as well as the kind of traffic moving through the USB controller. A recommended approach
is first to try leaving the aging mechanism disabled and see if the USB meets performance requirements.
If USB performance does not meet application requirements, try the following setting:
Raising AGE_CNT_THRESH benefits the other controllers on the system bus by reducing the frequency
that this USB controller raises its priority to the arbiter.
21.3.2.25 Priority Control Register (PRI_CTRL)—Non-EHCI
The priority control register (PRI_CTRL) enables dynamic priority elevation as configured in the
AGE_CNT_THRESH register. Note that this register uses big-endian byte ordering and is not defined in
the EHCI specification.
21-38
Offset 0x408
Reset
Offset 0x40C
Reset
18–31
29–31
0–17
0–27
Bits
Bits
28
W
R
W
R
0
0
Set PRI_CTRL[pri_en] to 1.
Set AGE_CNT_THRESH to 80.
Threshold
pri_en
Name
Name
Reserved, should be cleared.
High priority enable.
0 Normal operation. USB has default (low) priority.
1 High priority enabled.
Reserved.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved, should be cleared
Aging counter threshold value.
Table 21-32. AGE_CNT_THRESH Register Field Descriptions
Figure 21-30. Age Count Threshold (AGE_CNT_THRESH)
Table 21-33. PRI_CTRL Register Field Descriptions
Figure 21-31. Priority Control (PRI_CTRL)
All zeros
All zeros
Description
Description
17 18
Threshold
Freescale Semiconductor
27
Access: Read/Write
Access: Read/Write
pri_en
28
29
31
31

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