MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 747

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SRAMs will mostly be used by performance-critical applications, we assume here that, typically, the
maximum width of the local bus of 32 bits will be used.
ZBT SRAMs allow different configurations. For the local bus, the burst order should be set to linear burst
order by tying the mode pin to GND. CKE should also be tied to ground.
ZBT SRAMs perform four-beat bursts. Because the eLBC generates eight-beat transactions (for 32-bit
ports) the UPM breaks down each burst into two consecutive four-beat bursts. The internal address
generator of the eLBC generates the new LA bits for each burst. In other words, because linear burst is
used on the SRAM, the device itself bursts with the burst addresses of [0:1:2:3]. The local bus always
generates linear bursts and expects [0:1:2:3:4:5:6:7]. Therefore, two consecutive linear bursts of the ZBT
SRAM with {A27, A28} = {0,0} for the first burst, and {A27, A28} = {1,0} for the second burst give the
desired burst pattern.
The UPM also supports single beat accesses. Because the ZBT SRAM does not support this and always
responds with a burst, the UPM pattern has to take care that data for the critical beat is provided (for write)
or sampled (for read), and that the rest of the burst is ignored (by negating WE). The UPM controller
basically has to wait for the end of the SRAM burst to avoid bus contention with further bus activities.
Freescale Semiconductor
Local Bus Interface
LAD[0:31
LBS[0:3]
LDP[0:3]
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
LGPL0
LGPL1
LGPL2
LCS n
GPIO
LALE
LCLK
LA n
Latch
Figure 13-81. Interface to ZBT SRAM
BW[0:1]
DATA[0:15]
OE
CE
ADV/LD
WE
ZZ
BW[0:1]
MODE
CKE
CLK
SA[19:0]
DQ[0:17]
1M
SRAM
ZBT
18
DP[0:1]
BW[2:3]
DATA[16:31]
Enhanced Local Bus Controller
OE
CE
ADV/LD
WE
ZZ
BW[0:1]
MODE
CKE
CLK
SA[19:0]
DQ[0:17]
1M
SRAM
ZBT
18
DP[2:3]
13-105