MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 417

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The registers in
multi-core device. The OpenPIC interface specifies that a copy of these registers be available to each core
at the same physical address by using the ID of the processor core that initiates the transaction to determine
the set of per-CPU registers to access.
These addresses, shown in
in what is called the private access space. This duplication allows user code to execute correctly in an
multiprocessor environment without needing to know which core it is running on. On a single-core device,
each register has two addresses, one in the normal address space and one in the private access space. It is
included on even single-core devices to simplify the porting of such code.
Figure 9-44
accessing a register normally, each core sources a different address. However, when accessing the same
register using the per-CPU address space, each core sources the same address.
Freescale Semiconductor
shows how the duplicated registers are addressed in a four-core device Note that when
Table 9-44
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 9-44. Per-CPU Registers—Private Access Address Offsets
Interprocessor 0 dispatch register (IPIDR0)
Interprocessor 1 dispatch register (IPIDR1)
Interprocessor 2 dispatch register (IPIDR2)
Interprocessor 3 dispatch register (IPIDR3)
Current task priority register (CTPR)
Who am I register (WHOAMI0)
Interrupt acknowledge register (IACK)
End of interrupt register (EOI)
Table
are called per-CPU registers because they are duplicated for each core in a
9-44, appear in the memory map at the same offset for every processor
Register Name
0x00A0
0x00B0
0x0040
0x0050
0x0060
0x0070
0x0080
0x0090
Offset
Programmable Interrupt Controller (PIC)
9-47