MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1129

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17-24
Freescale Semiconductor
Bits
0–7
10
11
12
13
14
15
16
17
18
19
20
8
9
CDNSCIE Completion with data not successful interrupt enable. When this bit is set and PEX_ERR_DR[CDNSC] = 1
CRSNCIE CRS non configuration interrupt enable. When this bit is set and PEX_ERR_DR[CRSNC] = 1 generates an
PCACIE
CRSTIE
ICCAIE
CIEPIE
PNMIE
IACAIE
PCTIE
IOISIE
Name
MISIE
CISIE
—
—
describes the fields of the PCI Express error interrupt enable register.
Table 17-24. PCI Express Error Interrupt Enable Register Field Descriptions
Reserved
PCI Express completion time-out interrupt enable. When set and PEX_ERR_DR[PCT]=1 generates an
interrupt.
1 Enable PCI Express completion time-out interrupt generation
0 Disable PCI Express completion time-out interrupt generation
Reserved
PCI Express CA completion interrupt enable. When set and PEX_ERR_DR[PCAC]=1 generates an
interrupt.
1 Enable completion with CA status interrupt generation
0 Disable completion with CA status interrupt generation
PCI Express no map interrupt enable. When set and PEX_ERR_DR[PNM]=1 generates an interrupt.
1 Enable no map PCI Express packet interrupt generation
0 Disable no map PCI Express packet interrupt generation
generates an interrupt.
1 Enable completion with data non successful interrupt generation
0 Disable completion with data non successful interrupt generation
interrupt.
1 Enable CRS non configuration interrupt generation
0 Disable CRS non configuration interrupt generation
Invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA configuration access interrupt enable. When set and
PEX_ERR_DR[ICCA]=1 generates an interrupt.
1 Enable invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation
0 Disable invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation.
Invalid ATMU configuration access. When set and PEX_ERR_DR[IACA]=1 generates an interrupt.
1 Enable invalid ATMU configuration access interrupt generation
0 Disable invalid ATMU configuration access interrupt generation
CRS thresholded interrupt enable. When set and PEX_ERR_DR[CRST]=1 generates an interrupt.
1 Enable CRS threshold interrupt generation
0 Disable CRS threshold interrupt generation
Message invalid size interrupt enable. When set and PEX_ERR_DR[MIS]=1 generates an interrupt.
1 Enable invalid outbound message size interrupt generation
0 Disable invalid outbound message size interrupt generation
I/O invalid size interrupt enable. When set and PEX_ERR_DR[IOIS]=1 generates an interrupt.
1 Enable invalid outbound I/O size interrupt generation
0 Disable invalid outbound I/O size interrupt generation
Configuration invalid size interrupt enable. When set and PEX_ERR_DR[CIS]=1 generates an interrupt.
1 Enable invalid outbound configuration size interrupt generation
0 Disable invalid outbound configuration size interrupt generation
Configuration invalid EP interrupt enable. When set and PEX_ERR_DR[CIEP]=1 generates an interrupt.
1 Enable outbound configuration transaction while in EP mode interrupt generation
0 Disable outbound configuration transaction in EP mode interrupt generation
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Description
PCI Express Interface Controller
17-33