MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 812

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Figure 14-30
Table 14-35
14-64
Offset eTSEC1:0x2_4338;
Reset
16–21
1–15
Bit
22
23
24
0
W
R
eTSEC3:0x2_6338
GPI
0
Name
AND
CLE
REJ
GPI
—
Q
1
describes the fields of the RQFCR register.
describes the definition for the RQFCR register.
General purpose interrupt. When a property matches the value in the RQPROP entry at this index, and
REJ = 0 and AND = 0, the filer will instruct the Rx descriptor controller to set IEVENT[FGPI] when the
corresponding receive frame is written to memory.
If the timer is enabled (TMR_CTRL[TE] = 1), then TMR_PEVENT[RXP] will also be set.
Reserved, should be written with zero.
Receive queue index, from 0 to 63, inclusive, written into the Rx frame control block associated with the
received frame. When a property matches the value in the RQPROP entry at this index, and REJ = 0 and
AND = 0, the frame is sent to either RxBD ring 0 (if RCTRL[FSQEN] = 1) or the RxBD ring with index (Q mod
8) and the filing table search is terminated. In the case where RCTRL[FSQEN] = 0, 8 virtual receive queues
are overlaid on every RxBD ring, and software needs to consult the RQ field of the Rx frame control block to
determine which virtual receive queue was chosen.
Cluster entry/exit (used in combination with AND bit). This bit brackets clusters, marking the start and end
entries of a cluster. Clusters cannot be nested.
0 Regular RQCTRL entry.
1 If entry matches and AND = 1, treat subsequent entries as belonging to a nested cluster and enter the
Reject frame. This bit and its specified action are ignored if AND = 1.
0 If entry matches, accept frame and file it to RxBD ring Q.
1 If entry matches, reject frame and discard it, ignoring Q.
Match this entry and the next entry as a pair.
0 Match property[PID] against RQPROP, independent of the next entry.
1 Match property[PID] against RQPROP. If matched and CLE = 0, attempt to match next entry, otherwise,
cluster; otherwise skip all entries up to and including the next cluster exit. If AND = 0, exit current cluster.
skip all entries up to and including the entry with AND = 0. If matched and CLE = 1, enter cluster of entries,
otherwise, skip all entries up to and including the entry with CLE = 1 (cluster exit).
Figure 14-30. Receive Queue Filer Table Control Register Definition
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Table 14-35. RQFCR Field Descriptions
(undefined)
15 16
Description
Q
21
CLE REJ AND CMP —
22
23
24
Freescale Semiconductor
25 26 27 28
Access: Read/Write
PID
31