MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 309

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8-22
8.4.1.17
The DDR SDRAM initialization extended address register, shown in
address that is used for the data strobe to data skew adjustment and automatic CAS to preamble calibration
after POR.
Table 8-23
Freescale Semiconductor
Offset 0x14C
Reset
28–31
Offset 0x148
Reset
0–31
1–27
Bits
Bits
0
W
R
W
R
UIA
0
0
INIT_EXT_ADDR Initialization extended address. Represents the extended address that is used for the data strobe
INIT_ADDR Initialization address. Represents the address that is used for the data strobe to data skew adjustment
Name
describes the DDR_INIT_ADDR fields.
describes the DDR_INIT_EXT_ADDR fields.
1
Figure 8-17. DDR Initialization Address Configuration Register (DDR_INIT_ADDR)
Name
DDR Initialization Enable Extended Address (DDR_INIT_EXT_ADDR)
UIA
—
Figure 8-18. DDR Initialization Extended Address Configuration Register
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
and automatic CAS to preamble calibration at POR. This address is written to during the initialization
sequence.
Use initialization address.
0 Use the default address for training sequence as calculated by the controller. This is the first
1 Use the initialization address programmed in DDR_INIT_ADDR and DDR_INIT_EXT_ADDR.
Reserved, should be cleared.
to data skew adjustment and automatic CAS to preamble calibration at POR. This extended
address is written to during the initialization sequence.
Table 8-23. DDR_INIT_EXT_ADDR Field Descriptions
valid address in the first enabled chip select.
Table 8-22. DDR_INIT_ADDR Field Descriptions
(DDR_INIT_EXT_ADDR)
—
INIT_ADDR
All zeros
All zeros
Description
Description
Figure
8-18, provides the extended
27 28
DDR_INIT_EXT_ADDR
DDR Memory Controller
Access: Read/Write
Access: Read/Write
8-35
31
31