MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 546

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0x3_2050
Reset
Security Engine (SEC) 3.0
10.7.4.8
The DEU end of message register, shown in
message block has been written to the input FIFO (in channel-driven access, this signaling is done
automatically). The DEU will not process the last block of data in its input FIFO until this register is
written. Once the end of message register is written, the DEU processes any remaining data in the input
FIFO and generates the done interrupt.
The value written to this register does not matter. A read of this register always returns a zero value.
10-116
W
R
Bits
57
58
59
60
61
62
63
0
DEU End of Message Register
Name
OFE
OFU
OFO
IFO
IFE
IFU
AE
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-52. DEU Interrupt Mask Register Field Descriptions
Address Error. An illegal read or write address was detected within the DEU address space.
0 Address error enabled
1 Address error disabled
Output FIFO Error. The DEU output FIFO was detected non-empty upon write of DEU data size
register
0 Output FIFO non-empty error enabled
1 Output FIFO non-empty error disabled
Input FIFO Error. The DEU input FIFO was detected non-empty upon generation of done
interrupt
0 Input FIFO non-empty error enabled
1 Input FIFO non-empty error disabled
Input FIFO Underflow. The DEU input FIFO was read while empty.
0 Input FIFO Underflow error enabled
1 Input FIFO Underflow error disabled
Input FIFO Overflow. The DEU input FIFO was pushed while full.
0 Input FIFO overflow error enabled
1 Input FIFO overflow error disabled
Note: When operated through channel-controlled access, the SEC implements flow control,
Output FIFO Underflow. The DEU output FIFO was read while empty.
0 Output FIFO underflow error enabled
1 Output FIFO underflow error disabled
Output FIFO Overflow. The DEU output FIFO was pushed while full.
0 Output FIFO Overflow error enabled
1 Output FIFO Overflow error disabled
and FIFO size is not a limit to data input. When operated through host-controlled access,
the DEU cannot accept FIFO inputs larger than 256 bytes without overflowing.
Figure 10-63. DEU End of Message Register
Figure
10-63, is used to signal to the DEU that the final
All zeros
—
Description
Freescale Semiconductor
Access: Write only
63