MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 256

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM
6-36
icbtls_L2
Cache-inhibited instruction
fetch
Cacheable load (4-state)
Cacheable lwarx (4-state)
dcbt_L1 (4-state)
dcbtls_L1 (4-state)
Cache-inhibited load
Cache-inhibited lwarx
Writeback Store
Writeback stwcx
Cacheable load (3-state)
Cacheable lwarx (3-state)
dcbt_L1 (3-state)
dcbtls_L1 (3-state)
dcbt_L2
dcbtst_L2
dcbtst_L1
dcbtstls_L1
Source of Transaction
Table 6-27. State Transitions Due to Core-Initiated Transactions (continued)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Initial States
dL1
N/A
dL1
N/A
N/A
dL1
dL1
dL1
dL1
dL1
I,E
I,E
L1
I
I
I
I
I
E/EL
E/EL
N/A
N/A
N/A
EL
EL
EL
EL
EL
EL
EL
L2
I/T
I/T
I/T
I/T
I/T
E
E
T
E
T
E
E
T
E
T
E
I
I
I
I
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Hit
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
L2
Final States
N/A
N/A
N/A
EL
E/I
E/I
E/I
E/I
E/I
E/I
E/I
L1
M
M
M
M
M
M
E
E
E
E
E
E
E
E
I
I
I
I
I
I
I
same L2CTL[L2DO] = 1
same L2CTL[L2DO] = 0
same L2CTL[L2IO] = 1
same L2CTL[L2IO] = 0
same L2 allocates when a line is cast out of L1.
same
same L2CTL[L2IO] = 0
same
N/A
N/A
N/A
EL
EL
EL
EL
EL
L2
T
T
E
T
T
T
T
E
T
I
I
I
I
I
I
I
L2CTL[L2DO] = 1
L2CTL[L2DO] = 1
L2CTL[L2DO] = 0
L2CTL[L2DO] = 0
L2CTL[L2DO] = 0. Restore locked line in L2 with
valid data from bus
No L1/L2 effect
L2CTL[L2IO] = 1
L2CTL[L2IO] = 1
L2CTL[L2IO] = 0
L2CTL[L2IO] = 0. Restore locked line in L2 with
valid data from bus
No L1/L2 effect
No L2 effect
L2CTL[L2IO] = 1
L2CTL[L2IO] = 1
L2CTL[L2IO] = 1
L2CTL[L2IO] = 1
L2CTL[L2IO] = 0
L2CTL[L2IO] = 0. Restore locked line with valid
data from bus
Comments
Freescale Semiconductor