MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 671

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0x0_50B8
Reset
Reset
13.3.1.11 Transfer Error Interrupt Enable Register (LTEIR)
The transfer error interrupt enable register (LTEIR), shown in
error/event reporting through the eLBC internal interrupt mechanism. Software should clear pending
errors/events in LTESR before enabling interrupts. After an interrupt has occurred, clearing relevant
LTESR error/event bits negates the interrupt.
Table 13-18
Freescale Semiconductor
13–29
Bits
Bits
12
30
31
W
W
0
1
R
R
BMI
16
0
UCCD UPM Run pattern command completion checking disable.
Name
Name
CCD
FCTI
CSD
BMI
—
FCTI PARI
describes LTEIR fields.
1
Chip select error checking disable.
0 Chip select error checking is enabled.
1 Chip select error checking is disabled.
Reserved
0 UPM Run pattern command completion checking is enabled.
1 UPM Run pattern command completion checking is disabled.
FCM command completion checking disable.
0 Command completion checking is enabled.
1 Command completion checking is disabled.
Bus monitor error interrupt enable.
0 Bus monitor error reporting is disabled.
1 Bus monitor error reporting is enabled.
FCM command time-out interrupt enable.
0 FCM command time-out error reporting is disabled.
1 FCM command time-out error reporting is enabled.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
Figure 13-15. Transfer Error Interrupt Enable Register (LTEIR)
3
Table 13-17. LTEDR Field Descriptions (continued)
—
4
Table 13-18. LTEIR Field Descriptions
WPI
5
6
—
—
7
All zeros
All zeros
WARA RAWA
Description
Description
8
Figure
9
10
13-15, is used to send or block
—
11
CSI
12
Enhanced Local Bus Controller
13
29
Access: Read/Write
UCCI
—
30
13-29
CCI
15
31