MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 288

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
Table 8-7
8-14
13–15
16–17
18–20
21–23
9–11
Bits
1–7
12
0
8
ROW_BITS_CS_ n Number of row bits for SDRAM on chip select n . See
BA_BITS_CS_ n
ODT_WR_CFG
describes the CSn_CONFIG register fields.
ODT_RD_CFG
CS_ n _EN
AP_ n _EN
Name
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Chip select n enable
0 Chip select n is not active
1 Chip select n is active and assumes the state set in CS n _BNDS.
Reserved
Chip select n auto-precharge enable
0 Chip select n is only auto-precharged if global auto-precharge mode is enabled
1 Chip select n always issues an auto-precharge for read and write transactions.
3 cycles for ODT_RD_CFG to be enabled. ODT should only be used with DDR2 or DDR3
memories.
000 Never assert ODT for reads
001 Assert ODT only during reads to CS n
010 Assert ODT only during reads to other chip selects
011 Assert ODT only during reads to other DIMM modules. It is assumed that CS0 and CS1 are
100 Assert ODT for all reads
101–111 Reserved
Reserved
ODT for writes configuration. Note that write latency plus additive latency must be at least
3 cycles for ODT _WR_CFG to be enabled. ODT should only be used with DDR2 or DDR3
memories.
000 Never assert ODT for writes
001 Assert ODT only during writes to CS n
010 Assert ODT only during writes to other chip selects
011 Assert ODT only during writes to other DIMM modules. It is assumed that CS0 and CS1
100 Assert ODT for all writes
101–111 Reserved
Number of bank bits for SDRAM on chip select n . These bits correspond to the sub-bank bits
driven on MBA n in
00 2 logical bank bits
01 3 logical bank bits
10–11 Reserved
Reserved
000 12 row bits
001 13 row bits
010 14 row bits
011 15 row bits
100 16 row bits
101–111 Reserved
ODT for reads configuration. Note that CAS latency plus additive latency must be at least
(DDR_SDRAM_INTERVAL[BSTOPRE] = 0).
on the same DIMM module, whereas CS2 and CS3 are on a separate DIMM module.
are on the same DIMM module, whereas CS2 and CS3 are on a separate DIMM module.
Table 8-7. CS n _CONFIG Field Descriptions
Table
8-55and
Table
8-55.
Description
Table
8-55and
Table 8-55
Freescale Semiconductor
for details.