MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 811

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.3.3.6
RQFAR, shown in
received queue filer table. Each table entry occupies a pair of 32-bit words, denoted RQCTRL and
RQPROP. To access the RQCTRL and RQPROP words of entry n, write n to RQFAR. Then read or write
the indexed RQCTRL and RQPROP words by reading or writing the RQFCR and RQFPR registers,
respectively.
Table 14-34
14.5.3.3.7
RQFCR is accessed to read or write the RQCTRL words in entries of the receive queue filer table. The
table entries are described in greater detail in
through RQFCR is defined by the current value of RQFAR.
Freescale Semiconductor
24–25
26–31
24–31
0–23
Bits
Bits
Offset eTSEC1:0x2_4334;
Reset
W
R
B3OFFSET Offset relative to the header defined by B3CTL that locates byte 3 of property ARB. An effective offset
RQFAR Current index of receive queue filer table, which spans a total of 256 entries.
eTSEC3:0x2_6334
Name
0
B3CTL
Name
—
describes the fields of the RQFAR register.
Receive Queue Filer Table Address Register (RQFAR)
Receive Queue Filer Table Control Register (RQFCR)
Reserved
Figure 14-29. Receive Queue Filer Table Address Register Definition
Figure
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Location of byte 3 of property ARB.
00 Byte 3 is not extracted, and appears as zero in property ARB.
01 Byte 3 is located in the received frame at offset (B3OFFSET – 8) bytes from the first byte of the
10 Byte 0 is located in the received frame at offset B3OFFSET bytes from the byte after the last byte of
11 Byte 0 is located in the received frame at offset B3OFFSET bytes from the byte after the last byte of
of zero points to the first byte of the specified header.
Ethernet DA. In non-FIFO modes, a negative effective offset points to bytes of the standard Ethernet
preamble. Values of B3OFFSET less than 8 are reserved in FIFO modes.
the layer 2 header.
the layer 3 header.
14-29, contains the index of the current, indirectly accessible entry of the
Table 14-33. RBIFX Field Descriptions (continued)
Table 14-34. RQFAR Field Descriptions
—
Section 14.6.5.2, “Receive Queue Filer.”
All zeros
Description
Description
Enhanced Three-Speed Ethernet Controllers
23 24
The word accessed
Access: Read/Write
RQFAR
14-63
31