MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1139

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

memory request header; the upper half of the 64-bit address for a 4 DW memory request header or the
32-bit address for a 3 DW memory request header is captured in PEX_ERR_CAP_R2.
17.3.7
There are two methods of accessing the PCI Express configuration header:
17.3.7.1
To access internal configuration space, software must rely on the PCI Express configuration access register
(PEX_CONFIG_ADDR/ PEX_CONFIG_DATA) mechanism. To access external configuration space,
software can either use configuration access registers or the outbound ATMU mechanism. For the
configuration access register method, a value must be written to the PEX_CONFIG_ADDR register that
specifies the targeted PCI Express bus, the targeted device on that bus, the targeted function within the
device, and the configuration register in that device that should be accessed. The PCI Express controller’s
bus number is obtained from the PCI Express configuration header (type 1). Then either a write or a read
to the PEX_CONFIG_DATA register triggers the actual write or read cycle to the configuration space.
Note that accesses to the little-endian PCI Express configuration space must be properly formatted. See
Section 17.4.1.2.1, “Byte Order for Configuration
Note that external configuration transactions should not be attempted until the link has successfully
trained. Software can poll the LTSSM state status register (PEX_LTSSM_STAT) to check the status of link
training before issuing external configuration requests.
17.3.7.1.1
There are two types of configuration transactions (Type 0 and Type 1) needed to support hierarchical
bridges.
Freescale Semiconductor
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PCI Express outbound ATMU window
PCI Express configuration access registers (PEX_CONFIG_ADDR/PEX_CONFIG_DATA)
If the targeted bus number, and targeted device number equal to the PCI Express controller’s bus
number and device number, and the targeted function number is zero, then an internal PCI Express
configuration cycle access is performed.
0–31
Bits
PCI Express Configuration Space Access
RC Configuration Register Access
PCI Express Configuration Access Register Mechanism
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Name
GH3
Table 17-36. PEX Error Capture Register 3 Field Descriptions
External Source, Inbound Memory Request Transaction
PEX fourth DW (4-byte) header. This field contains the fourth DW (4-byte) of the
captured PCI Express packet header.
24–31
16–23
8–15
6–7
0-5
Address[31:24]
Address[23:16]
Address[15:8]
Reserved
Address[7:2]
Transactions,” for more information.
Description
PCI Express Interface Controller
17-43