MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1345

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.2.1
The module executes the command indicated in this register.
Freescale Semiconductor
Offset 0x140
Reset
Reset
31–24
23–16
Bits
15
14
13
12
11
10
W
W
R
R
FS2 ATDTW SUTW
31
15
0
0
ATDTW Add dTD TripWire. This is a non-EHCI bit. Used as a semaphore when a dTD is added to an active (primed)
SUTW
Name
ASPE
FS2
ITC
—
—
—
USB Command Register (USBCMD)
14
0
n
Reserved, should be cleared.
Interrupt threshold control. The system software uses this field to set the maximum rate at which the USB
module will issue interrupts. ITC contains the maximum interrupt interval measured in microframes. Valid
values are shown below.
0x00 Immediate (no threshold)
0x01 1 microframe
0x02 2 microframes
0x04 4 microframes
0x08 8 microframes
0x10 16 microframes
0x20 32 microframes
0x40 40 microframes
See bits 3–2 below. This is a non-EHCI bit.
endpoint. This bit is set and cleared by software. This bit shall also be cleared by hardware when is state
machine is hazard region where adding a dTD to a primed endpoint may go unrecognized. More information
on the use of this bit is described in
Setup tripwire. This is a non-EHCI bit. Used as a semaphore when the 8 bytes of setup data read extracted
from a QH by the DCD. If the setup lockout mode is off (See USBMODE) then there exists a hazard when
new setup data arrives and the DCD is copying setup from the QH for a previous setup packet. This bit is
set and cleared by software and will be cleared by hardware when a hazard exists. More information on the
use of this bit is described in
Reserved, should be cleared.
Asynchronous schedule park mode enable. This bit defaults to a 1 and is R/W. Software uses this bit to
enable or disable park mode.
0 Disabled
1 Enabled
Reserved, should be cleared.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
13
0
n
12
—
0
0
Table 21-9. USBCMD Register Field Descriptions
Figure 21-8. USB Command Register (USBCMD)
—
ASPE
11
0
1
—
10
0
0
Section 21.9.2, “Device Operation.”
0
1
9
Section 21.9.2, “Device Operation.”
ASP
24
0
1
8
Description
LR
23
0
0
7
IAA
0
n
6
ASE
0
0
5
PSE
0
0
4
ITC
Universal Serial Bus Interfaces
FS1
1
0
3
FS0
0
0
2
Access: Mixed
RST
0
0
1
21-11
RS
16
0
0
0