MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 981

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-190
Freescale Semiconductor
describes the register initializations required to configure the eTSEC in 8-bit FIFO mode.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(Rx enable = 1, Tx enable = 1, enable flow control and CRC, 8-bit mode)
RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Table 14-190. 8-Bit FIFO Mode Register Initialization Steps
TBASE0–TBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Initialize (Empty) Receive Descriptor ring and fill with empty buffers
Initialize (Empty) transmit descriptor ring and fill buffers with data
MACCFG2[0000_0000_0000_0000_0111_0000_0000_0000]
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
FIFOCFG[0000_0000_0000_0000_1100_0000_0000_0000]
FIFOCFG[0000_0000_0000_0000_0000_0000_0000_1000]
FIFOCFG[0000_0000_0000_0000_0011_0000_1101_1000]
ECNTRL[0000_0000_0000_0000_1000_0000_0000_0000]
(Reset RX = 1, reset Tx = 1, Rx enable = 0, Tx enable = 0)
(Reset RX = 0, reset Tx = 0, Rx enable = 0, Tx enable = 0)
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
(Used to set up FIFO mode = 1, and statistics enable = 0)
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Ensure MACCFG2 is set to default values.
Initialize DMACTRL (Optional)
Enable Rx and Tx over FIFO,
Initialize RBASE0–RBASE7,
Initialize TBASE0–TBASE7,
Initialize RCTRL (Optional)
Initialize IMASK (Optional)
Enable Transmit Queues
Enable Receive Queues
Clear FIFO Soft_Reset,
Clear IEVENT register,
Set FIFO Soft_Reset,
Initialize ECNTRL,
Initialize RQUEUE
Initialize TQUEUE
Enhanced Three-Speed Ethernet Controllers
14-233