MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1118

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.5.1.3
The PCI Express outbound window base address registers, shown in
for the windows which are translated to the external address space. Addresses for outbound transactions
are compared to these windows. If such a transaction does not fall within one of these spaces the
transaction is forwarded through a default register set.
Table 17-17
17.3.5.1.4
The PCI Express outbound window attributes registers, shown in
the window sizes to translate and other attributes for the translations. 64 Gbytes is the largest window size
allowed.
Offset 0xC10
Reset 1
17-22
12–31
8–11
Bits
0–7
Offset Window 1: 0xC28
Reset
W
R EN
W
R
0
Window 2: 0xC48
Window 3: 0xC68
Window 4: 0xC88
WBEA Window base extended address. Source address which is the starting point for the outbound translation
Name
Table 17-17. PCI Express Outbound Window Base Address Register n Field Descriptions
WBA
0
Figure 17-17
Figure 17-16. PCI Express Outbound Window Base Address Registers (PEXOWBAR n )
—
—
1
0
describes the fields of the PCI Express outbound window base address registers.
Figure 17-17. PCI Express Outbound Window Attributes Register 0 (PEXOWAR0)
PCI Express Outbound Window Base Address Registers
(PEXOWBAR n )
PCI Express Outbound Window Attributes Registers (PEXOWAR n )
2
0
Reserved
window. The window must be aligned based on the size selected in the window size bits. Correspond to
internal platform address bits [0:3]. (where 0 is the msb of the internal platform address)
Window base address. Source address which is the starting point for the outbound translation window. The
window must be aligned based on the size selected in the window size bits. This corresponds to internal
platform address bits [4:23].
ROE NS
—
0
3
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
shows the outbound window attributes register 0 (PEXOWAR0).
0
4
0 0 0 0
5
—
7
7
8
8
WBEA
TC
0
10 11 12
0
11 12
—
0
0
1 0 0
RTT
All zeros
Description
15 16
0
WTT
1 0
Figure 17-17
19 20
0
Figure
0
WBA
0 0 0 0
17-16, select the base address
—
and
Figure
Freescale Semiconductor
25 26
0
Access: Read/Write
1 0 0 0 1
17-18, define
Access: Mixed
OWS
31
31
1