MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 824

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.5.2
The MACCFG2 register is written by the user.
register.
Table 14-44
14-76
Offset eTSEC1:0x2_4504;
Reset
Reset 0 1 1 1 0 0
16–19
20–21
22–23
0–15
Bits
24
25
W
W
R
R Preamble
eTSEC3:0x2_6504
16
0
Length
PreAM RxEN User defined preamble enable for received frames. This bit is cleared by default.
PreAM TxEN User defined preamble enable for transmitted frames. This bit is cleared by default.
Preamble
I/F Mode
Length
Name
describes the fields of the MACCFG2 register.
19 20 21
—
—
MAC Configuration 2 Register (MACCFG2)
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
This field determines the length in bytes of the preamble field preceding each Ethernet start-of-frame
delimiter byte. Values from 0x3 to 0xF are supported by the controller. The default value of 0x7 should
not be altered in order to guarantee reliable operation with IEEE 802.3 compliant hardware.
Reserved
This field determines the type of interface to which the MAC is connected. Its default is 00.
00 Reserved bit mode (not supported) (10 Mbps GENDEC/GPSI)
01 Nibble mode (MII) (10/100 Mbps MII/RMII)
10 Byte mode (GMII/TBI) (1000 MbpsGMII/TBI). Reserved if neither GMII or TBI are supported.
11 Reserved
0 The MAC skips the Ethernet preamble without returning it.
1 The MAC recovers the received Ethernet preamble and passes it to the driver at the start of each
0 The MAC generates a standard Ethernet preamble.
1 If a user-defined preamble has been passed to the MAC it is transmitted instead of the standard
22
Mode
0
I/F
received frame. If the preamble is less than 7 bytes, 0’s are prepended to pad it to 7 bytes. Not
applicable to FIFO or RMII 10/100 modes.
preamble. Otherwise the standard Ethernet preamble is generated. The Preamble Length field
should be left at its default setting if a user-defined preamble is transmitted. Not applicable to FIFO
or RMII 10/100 modes.
23
0
PreAmRxEN PreAmTxEN
Figure 14-40. MACCFG2 Register Definition
Table 14-44. MACCFG2 Field Descriptions
24
0
25
0
Figure 14-40
All zeros
Frame
Huge
—
26
0
Description
describes the definition for the MACCFG2
Length
check
27
0
MPEN
28
0
PAD/CRC CRC EN
29
0
Freescale Semiconductor
Access: Read/Write
30
0
Duplex
Full
15
31
0