MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 304

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
Table 8-16
8.4.1.12
The DDR SDRAM mode control register, shown in
tasks:
Table 8-17
register to accomplish the above tasks.
Table 8-17
8-30
Offset 0x120
Reset
16–31
0–15
Bits
W
•
•
•
•
R
MD_EN
Issue a mode register set command to a particular chip select
Issue an immediate refresh to a particular chip select
Issue an immediate precharge or precharge all command to a particular chip select
Force the CKE signals to a specific value
ESDMODE2 Extended SDRAM mode 2. Specifies the initial value loaded into the DDR SDRAM extended 2 mode
ESDMODE3 Extended SDRAM mode 3. Specifies the initial value loaded into the DDR SDRAM extended 3 mode
0
describes the DDR_SDRAM_MODE_2 fields.
describes the fields of this register.
describes the DDR_SDRAM_MD_CNTL fields.
Name
DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)
1
CS_SEL
Note that MD_EN, SET_REF, and SET_PRE are mutually exclusive; only
one of these fields can be set at a time.
Figure 8-13. DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)
2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
register. The range and meaning of legal values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during the DDR SDRAM initialization sequence),
MA[0] presents the lsb bit of ESDMODE2, which, in the big-endian convention shown in
corresponds to ESDMODE2[15]. The msb of the SDRAM extended mode 2 register value must be
stored at ESDMODE2[0].
register. The range of legal values of legal values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the
lsb of ESDMODE3, which, in the big-endian convention shown in
ESDMODE3[15]. The msb of the SDRAM extended mode 3 register value must be stored at
ESDMODE3[0].
3
— MD_SEL SET_REF SET_PRE CKE_CNTL WRCW
4
Table 8-16. DDR_SDRAM_MODE_2 Field Descriptions
5
7
8
Table 8-18
9
NOTE
Figure
All zeros
10
Description
shows the user how to set the fields of this
8-13, allows the user to carry out the following
11
12
13
—
Figure
15 16
8-12, corresponds to
Freescale Semiconductor
MD_VALUE
Access: Read/Write
Figure
8-12,
31