MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 528

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
Writes to the input FIFO go first to a staging register which can be written by byte, word (4 bytes), or dword
(8 bytes). When all 8 bytes of the staging register have been written, the entire dword is automatically
enqueued into the FIFO. If any byte is written twice between enqueues, it causes an error interrupt of type
AE from the EU. When writing the last portion of data, it is not necessary to write all 8 bytes. Any last
bytes remaining in the staging register are automatically padded with zeros and forced into the input FIFO
when the AFEU end of message register is written.
The output FIFO is readable by byte, word, or dword. When all 8 bytes of the head dword have been read,
that dword is automatically dequeued from the FIFO so that the next dword (if any) becomes available for
reading. If any byte is read twice between dequeues, it causes an error interrupt of type AE from the EU.
Overflows and underflows caused by reading or writing the AFEU FIFOs are reflected in the AFEU
interrupt status register.
10.7.3
This section contains details about the cyclical redundancy check unit (CRCU), including modes of
operation, status and control registers, and FIFO.
Most of the registers described here would not normally be accessed by the host. They are documented
here mainly for debug purposes. In typical operation, the CRCU is used through channel-controlled access,
which means that most reads and writes of CRCU registers are directed by the SEC channels. Driver
software would perform host-controlled register accesses only on a few registers for initial configuration
and error handling.
10.7.3.1
This EU includes an ICV checking feature, that is, it can verify a message/CRC pair by calculating a raw
CRC and comparing it to the polynomial specific residue. The pass/fail result of this check can be returned
to the host either by interrupt by a writeback of EU status fields into host memory, but not by both methods
at once.
To signal the ICV checking result by status writeback, turn on either the IWSE bit or AWSE bit in the
channel configuration register (see
the CICV fail (CICVF) bit in the interrupt mask register (see
Register”). In this case the normal done signaling (by interrupt or writeback) is undisturbed.
To signal the ICV checking result by interrupt, unmask the CICVF bit in the interrupt mask register and
turn off the IWSE and AWSE bits in the channel configuration register. If there is no CRC mismatch, then
the normal done signaling (by interrupt or writeback) occurs. When there is an CRC mismatch, there is an
error interrupt to the host, but no done interrupt or writeback.
10.7.3.2
The mode register (shown in
the first register written. A context error is generated if this register is written after processing has begun.
10-98
Cyclical Redundancy Check Unit (CRCU)
ICV Checking in CRCU
CRCU Mode Register
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure
Section 10.4.4.1, “Channel Configuration Register
10-40) is used to program the function of the CRCU and is generally
Section 10.7.3.9, “CRCU Interrupt Mask
Freescale Semiconductor
(CCR)”), and mask